Analysis of the trade-off between voltage gain and frequency response of OTA designed using experimental data of omega-gate nanowire SOI MOSFETs (2023)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; ARAUJO, GUSTAVO VINICIUS DE - EP
- Unidade: EP
- DOI: 10.1109/SBMicro60499.2023.10302603
- Subjects: TRANSISTORES; CIRCUITOS ANALÓGICOS; MICROELETRÔNICA; MATERIAIS NANOESTRUTURADOS
- Agências de fomento:
- Language: Inglês
- Imprenta:
- Publisher: IEEE
- Publisher place: [Piscataway, N.J.]
- Date published: 2023
- Source:
- Título: SBMicro
- Conference titles: Symposium on Microelectronics Technology and Devices
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
ARAÚJO, Gustavo Vinicius de e MARTINO, João Antonio e AGOPIAN, Paula Ghedini Der. Analysis of the trade-off between voltage gain and frequency response of OTA designed using experimental data of omega-gate nanowire SOI MOSFETs. 2023, Anais.. [Piscataway, N.J.]: IEEE, 2023. Disponível em: https://doi.org/10.1109/SBMicro60499.2023.10302603. Acesso em: 23 jan. 2026. -
APA
Araújo, G. V. de, Martino, J. A., & Agopian, P. G. D. (2023). Analysis of the trade-off between voltage gain and frequency response of OTA designed using experimental data of omega-gate nanowire SOI MOSFETs. In SBMicro. [Piscataway, N.J.]: IEEE. doi:10.1109/SBMicro60499.2023.10302603 -
NLM
Araújo GV de, Martino JA, Agopian PGD. Analysis of the trade-off between voltage gain and frequency response of OTA designed using experimental data of omega-gate nanowire SOI MOSFETs [Internet]. SBMicro. 2023 ;[citado 2026 jan. 23 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302603 -
Vancouver
Araújo GV de, Martino JA, Agopian PGD. Analysis of the trade-off between voltage gain and frequency response of OTA designed using experimental data of omega-gate nanowire SOI MOSFETs [Internet]. SBMicro. 2023 ;[citado 2026 jan. 23 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302603 - Trade-off between channel length and mechanical stress in the operational transconductance amplifier designed with SOI FinFET
- Uniaxially strained silicon influence on two-stage operational transconductance amplifiers designed with SOI FinFET's
- Estudo de um amplificador operacional de transcondutância projetado com transistores de nanofios de porta ômega
- Analog circuit design using graded-channel SOI NMOSFETs
- Extraction of the interface charge density at the silicon substrate interface in SOI MOSFET's at cryogenic temperatures
- Extraction of the interface and oxide charge density in silicon-on-insulator MOSFETs
- Projeto de um processo CMOS com cavidade dupla e dimensões de porta de 2 um
- Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time
- Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation
- Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results
Informações sobre o DOI: 10.1109/SBMicro60499.2023.10302603 (Fonte: oaDOI API)
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