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Artigo de periodico
Threshold voltage extraction in Tunnel FETs (2014)
Ortiz-Conde, Adelmo; Martino, João Antonio ; Garcia- Sanchez, Francisco J.; Muci, Juan; Martino, João Antonio ; Agopian, Paula Ghedini Der ; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
ORTIZ-CONDE, Adelmo et al. Threshold voltage extraction in Tunnel FETs. Solid-State Electronics, v. 93, p. 49-55, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2013.12.010. Acesso em: 11 nov. 2024.
APA
Ortiz-Conde, A., Martino, J. A., Garcia- Sanchez, F. J., Muci, J., Martino, J. A., Agopian, P. G. D., & Claeys, C. (2014). Threshold voltage extraction in Tunnel FETs. Solid-State Electronics, 93, 49-55. doi:10.1016/j.sse.2013.12.010
NLM
Ortiz-Conde A, Martino JA, Garcia- Sanchez FJ, Muci J, Martino JA, Agopian PGD, Claeys C. Threshold voltage extraction in Tunnel FETs [Internet]. Solid-State Electronics. 2014 ; 93 49-55.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1016/j.sse.2013.12.010
Vancouver
Ortiz-Conde A, Martino JA, Garcia- Sanchez FJ, Muci J, Martino JA, Agopian PGD, Claeys C. Threshold voltage extraction in Tunnel FETs [Internet]. Solid-State Electronics. 2014 ; 93 49-55.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1016/j.sse.2013.12.010
Artigo de periodico
Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation (2014)
Caño de Andrade, Maria Glória; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Aoulaiche, Marc; Martino, João Antonio
Source: Microelectronics Reliability. Unidade: EP
Subjects: SILÍCIO, MICROELETRÔNICA
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ABNT
CAÑO DE ANDRADE, Maria Glória et al. Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation. Microelectronics Reliability, v. 54, n. 11, p. 2349-2354, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.microrel.2014.06.013. Acesso em: 11 nov. 2024.
APA
Caño de Andrade, M. G., Collaert, N., Simoen, E., Claeys, C., Aoulaiche, M., & Martino, J. A. (2014). Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation. Microelectronics Reliability, 54( 11), 2349-2354. doi:10.1016/j.microrel.2014.06.013
NLM
Caño de Andrade MG, Collaert N, Simoen E, Claeys C, Aoulaiche M, Martino JA. Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation [Internet]. Microelectronics Reliability. 2014 ; 54( 11): 2349-2354.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1016/j.microrel.2014.06.013
Vancouver
Caño de Andrade MG, Collaert N, Simoen E, Claeys C, Aoulaiche M, Martino JA. Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation [Internet]. Microelectronics Reliability. 2014 ; 54( 11): 2349-2354.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1016/j.microrel.2014.06.013
Artigo de periodico
Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs (2014)
Teixeira, Fernando Ferrari; Martino, João Antonio ; Bordallo, Caio Cesar Mendes ; Silveira, Marcilei Aparecida Guazzelli da; Agopian, Paula Ghedini Der ; Simoen, Eddy ; Claeys, Cor
Source: Journal of Integrated Circuits and Systems. Unidade: EP
Subjects: MICROELETRÔNICA, RAIOS X
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ABNT
TEIXEIRA, Fernando Ferrari et al. Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs. Journal of Integrated Circuits and Systems, v. 9, n. 2, p. 97-102, 2014Tradução . . Disponível em: https://doi.org/10.29292/jics.v9i2.394. Acesso em: 11 nov. 2024.
APA
Teixeira, F. F., Martino, J. A., Bordallo, C. C. M., Silveira, M. A. G. da, Agopian, P. G. D., Simoen, E., & Claeys, C. (2014). Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs. Journal of Integrated Circuits and Systems, 9( 2), 97-102. doi:10.29292/jics.v9i2.394
NLM
Teixeira FF, Martino JA, Bordallo CCM, Silveira MAG da, Agopian PGD, Simoen E, Claeys C. Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 97-102.[citado 2024 nov. 11 ] Available from: https://doi.org/10.29292/jics.v9i2.394
Vancouver
Teixeira FF, Martino JA, Bordallo CCM, Silveira MAG da, Agopian PGD, Simoen E, Claeys C. Parasitic conduction response to X-ray radiation in unstrained and strained triple-gate SOI MuGFETs [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 97-102.[citado 2024 nov. 11 ] Available from: https://doi.org/10.29292/jics.v9i2.394
Artigo de periodico
Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time (2014)
Nissimoff, Albert; Martino, João Antonio ; Aoulaiche, Marc; Veloso, Anabela; Witters, Liesbeth J.; Simoen, Eddy ; Claeys, Cor
Source: IEEE Electron Device Letters. Unidade: EP
Subjects: TRANSISTORES, MODELOS MATEMÁTICOS, CAPACITORES
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ABNT
NISSIMOFF, Albert et al. Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time. IEEE Electron Device Letters, v. 35, n. 6, p. 639-641, 2014Tradução . . Disponível em: https://doi.org/10.1109/led.2014.2319094. Acesso em: 11 nov. 2024.
APA
Nissimoff, A., Martino, J. A., Aoulaiche, M., Veloso, A., Witters, L. J., Simoen, E., & Claeys, C. (2014). Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time. IEEE Electron Device Letters, 35( 6), 639-641. doi:10.1109/led.2014.2319094
NLM
Nissimoff A, Martino JA, Aoulaiche M, Veloso A, Witters LJ, Simoen E, Claeys C. Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time [Internet]. IEEE Electron Device Letters. 2014 ; 35( 6): 639-641.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1109/led.2014.2319094
Vancouver
Nissimoff A, Martino JA, Aoulaiche M, Veloso A, Witters LJ, Simoen E, Claeys C. Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time [Internet]. IEEE Electron Device Letters. 2014 ; 35( 6): 639-641.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1109/led.2014.2319094
Artigo de periodico
Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation (2014)
Bordallo, Caio Cesar Mendes ; Martino, João Antonio ; Teixeira, Fernando Ferrari; Silveira, Marcilei Aparecida Guazzelli da; Agopian, Paula Ghedini Der ; Simoen, Eddy ; Claeys, Cor
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: RAIOS X, MICROELETRÔNICA
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ABNT
BORDALLO, Caio Cesar Mendes et al. Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation. Semiconductor Science and Technology, v. 29, n. 12, p. 125015, 2014Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/29/12/125015. Acesso em: 11 nov. 2024.
APA
Bordallo, C. C. M., Martino, J. A., Teixeira, F. F., Silveira, M. A. G. da, Agopian, P. G. D., Simoen, E., & Claeys, C. (2014). Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation. Semiconductor Science and Technology, 29( 12), 125015. doi:10.1088/0268-1242/29/12/125015
NLM
Bordallo CCM, Martino JA, Teixeira FF, Silveira MAG da, Agopian PGD, Simoen E, Claeys C. Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation [Internet]. Semiconductor Science and Technology. 2014 ; 29( 12): 125015.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1088/0268-1242/29/12/125015
Vancouver
Bordallo CCM, Martino JA, Teixeira FF, Silveira MAG da, Agopian PGD, Simoen E, Claeys C. Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation [Internet]. Semiconductor Science and Technology. 2014 ; 29( 12): 125015.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1088/0268-1242/29/12/125015
Artigo de periodico
Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation (2014)
Nicoletti, Talitha; Santos, Sara Dereste dos; Martino, João Antonio ; Aoulaiche, Marc; Veloso, Anabela; Claeys, Cor ; Simoen, Eddy ; Jurczak, Malgorzata
Source: Solid-State Electronics. Unidade: EP
Subjects: TEMPERATURA, MICROELETRÔNICA
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ABNT
NICOLETTI, Talitha et al. Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation. Solid-State Electronics, v. 91, p. 53-58, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2013.09.012. Acesso em: 11 nov. 2024.
APA
Nicoletti, T., Santos, S. D. dos, Martino, J. A., Aoulaiche, M., Veloso, A., Claeys, C., et al. (2014). Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation. Solid-State Electronics, 91, 53-58. doi:10.1016/j.sse.2013.09.012
NLM
Nicoletti T, Santos SD dos, Martino JA, Aoulaiche M, Veloso A, Claeys C, Simoen E, Jurczak M. Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation [Internet]. Solid-State Electronics. 2014 ; 91 53-58.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1016/j.sse.2013.09.012
Vancouver
Nicoletti T, Santos SD dos, Martino JA, Aoulaiche M, Veloso A, Claeys C, Simoen E, Jurczak M. Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation [Internet]. Solid-State Electronics. 2014 ; 91 53-58.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1016/j.sse.2013.09.012
Artigo de periodico
Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results (2014)
Nissimoff, Albert; Claeys, Cor ; Aoulaiche, Marc; Sasaki, Karen Lucia Mayumi; Simoen, Eddy ; Martino, João Antonio
Source: Journal of Integrated Circuits and Systems. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
NISSIMOFF, Albert et al. Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results. Journal of Integrated Circuits and Systems, v. 9, n. 2, p. 91-96, 2014Tradução . . Disponível em: https://doi.org/10.29292/jics.v9i2.393. Acesso em: 11 nov. 2024.
APA
Nissimoff, A., Claeys, C., Aoulaiche, M., Sasaki, K. L. M., Simoen, E., & Martino, J. A. (2014). Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results. Journal of Integrated Circuits and Systems, 9( 2), 91-96. doi:10.29292/jics.v9i2.393
NLM
Nissimoff A, Claeys C, Aoulaiche M, Sasaki KLM, Simoen E, Martino JA. Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 91-96.[citado 2024 nov. 11 ] Available from: https://doi.org/10.29292/jics.v9i2.393
Vancouver
Nissimoff A, Claeys C, Aoulaiche M, Sasaki KLM, Simoen E, Martino JA. Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results [Internet]. Journal of Integrated Circuits and Systems. 2014 ; 9( 2): 91-96.[citado 2024 nov. 11 ] Available from: https://doi.org/10.29292/jics.v9i2.393
Artigo de periodico
Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics (2014)
Santos, Sara Dereste dos; Martino, João Antonio ; Cretu, B; Strobel, V; Routoure, J.-M; Carin, R; Aoulaiche, Marc; Jurczak, Malgorzata; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Subjects: TEMPERATURA, MICROELETRÔNICA, SILÍCIO
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ABNT
SANTOS, Sara Dereste dos et al. Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics. Solid-State Electronics, v. 97, p. 14-22, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2014.04.034. Acesso em: 11 nov. 2024.
APA
Santos, S. D. dos, Martino, J. A., Cretu, B., Strobel, V., Routoure, J. -M., Carin, R., et al. (2014). Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics. Solid-State Electronics, 97, 14-22. doi:10.1016/j.sse.2014.04.034
NLM
Santos SD dos, Martino JA, Cretu B, Strobel V, Routoure J-M, Carin R, Aoulaiche M, Jurczak M, Claeys C. Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics [Internet]. Solid-State Electronics. 2014 ; 97 14-22.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1016/j.sse.2014.04.034
Vancouver
Santos SD dos, Martino JA, Cretu B, Strobel V, Routoure J-M, Carin R, Aoulaiche M, Jurczak M, Claeys C. Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics [Internet]. Solid-State Electronics. 2014 ; 97 14-22.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1016/j.sse.2014.04.034
Artigo de periodico
Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications (2014)
Sasaki, Karen Lucia Mayumi; Nicoletti, Talitha; Almeida, L M; Santos, Sara Dereste dos; Nissimoff, Albert; Aoulaiche, Marc; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: TRANSISTORES
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ABNT
SASAKI, Karen Lucia Mayumi et al. Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications. Solid-State Electronics, v. 97, p. 30-37, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2014.04.031. Acesso em: 11 nov. 2024.
APA
Sasaki, K. L. M., Nicoletti, T., Almeida, L. M., Santos, S. D. dos, Nissimoff, A., Aoulaiche, M., & Martino, J. A. (2014). Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications. Solid-State Electronics, 97, 30-37. doi:10.1016/j.sse.2014.04.031
NLM
Sasaki KLM, Nicoletti T, Almeida LM, Santos SD dos, Nissimoff A, Aoulaiche M, Martino JA. Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications [Internet]. Solid-State Electronics. 2014 ;97 30-37.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1016/j.sse.2014.04.031
Vancouver
Sasaki KLM, Nicoletti T, Almeida LM, Santos SD dos, Nissimoff A, Aoulaiche M, Martino JA. Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications [Internet]. Solid-State Electronics. 2014 ;97 30-37.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1016/j.sse.2014.04.031

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