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Filtros : "Indexado no INSPEC" "Solid-State Electronics" Limpar

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1 - 9 (9 records)

  • Artigo de periodico

    SOI technology characterization using SOI-MOS capacitor (2005)

    Sonnenberg, Victor ; Martino, João Antonio

    Source: Solid-State Electronics. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS MOS

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    • ABNT

      SONNENBERG, Victor e MARTINO, João Antonio. SOI technology characterization using SOI-MOS capacitor. Solid-State Electronics, 2005Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2004.06.010. Acesso em: 04 out. 2024.

    • APA

      Sonnenberg, V., & Martino, J. A. (2005). SOI technology characterization using SOI-MOS capacitor. Solid-State Electronics. doi:10.1016/j.sse.2004.06.010

    • NLM

      Sonnenberg V, Martino JA. SOI technology characterization using SOI-MOS capacitor [Internet]. Solid-State Electronics. 2005 ;[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/j.sse.2004.06.010

    • Vancouver

      Sonnenberg V, Martino JA. SOI technology characterization using SOI-MOS capacitor [Internet]. Solid-State Electronics. 2005 ;[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/j.sse.2004.06.010

  • Artigo de periodico

    Extraction of the oxide charge density at front and back interfaces of SOI nMOSFETs devices (2002)

    Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor

    Source: Solid-State Electronics. Unidade: EP

    Assunto: FILMES FINOS

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    • ABNT

      NICOLETT, Aparecido Sirley et al. Extraction of the oxide charge density at front and back interfaces of SOI nMOSFETs devices. Solid-State Electronics, n. 9, p. 1381-1387, 2002Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(02)00067-9. Acesso em: 04 out. 2024.

    • APA

      Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2002). Extraction of the oxide charge density at front and back interfaces of SOI nMOSFETs devices. Solid-State Electronics, ( 9), 1381-1387. doi:10.1016/s0038-1101(02)00067-9

    • NLM

      Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the oxide charge density at front and back interfaces of SOI nMOSFETs devices [Internet]. Solid-State Electronics. 2002 ;( 9): 1381-1387.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(02)00067-9

    • Vancouver

      Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the oxide charge density at front and back interfaces of SOI nMOSFETs devices [Internet]. Solid-State Electronics. 2002 ;( 9): 1381-1387.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(02)00067-9

  • Artigo de periodico

    Analog circuit design using graded-channel silicon-on-insulator nMOSFETs (2002)

    Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis

    Source: Solid-State Electronics. Unidade: EP

    Assunto: CIRCUITOS ANALÓGICOS

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    • ABNT

      PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs. Solid-State Electronics, v. 46, n. 8, p. 1215-1225, 2002Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(02)00020-5. Acesso em: 04 out. 2024.

    • APA

      Pavanello, M. A., Martino, J. A., & Flandre, D. (2002). Analog circuit design using graded-channel silicon-on-insulator nMOSFETs. Solid-State Electronics, 46( 8), 1215-1225. doi:10.1016/s0038-1101(02)00020-5

    • NLM

      Pavanello MA, Martino JA, Flandre D. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs [Internet]. Solid-State Electronics. 2002 ; 46( 8): 1215-1225.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(02)00020-5

    • Vancouver

      Pavanello MA, Martino JA, Flandre D. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs [Internet]. Solid-State Electronics. 2002 ; 46( 8): 1215-1225.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(02)00020-5

  • Artigo de periodico

    Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures (2001)

    Bellodi, Marcello; Martino, João Antonio

    Source: Solid-State Electronics. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS

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    • ABNT

      BELLODI, Marcello e MARTINO, João Antonio. Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures. Solid-State Electronics, v. 45, n. 5, p. 683-688, 2001Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(01)00099-5. Acesso em: 04 out. 2024.

    • APA

      Bellodi, M., & Martino, J. A. (2001). Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures. Solid-State Electronics, 45( 5), 683-688. doi:10.1016/s0038-1101(01)00099-5

    • NLM

      Bellodi M, Martino JA. Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures [Internet]. Solid-State Electronics. 2001 ; 45( 5): 683-688.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(01)00099-5

    • Vancouver

      Bellodi M, Martino JA. Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures [Internet]. Solid-State Electronics. 2001 ; 45( 5): 683-688.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(01)00099-5

  • Artigo de periodico

    Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs (2000)

    Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor

    Source: Solid-State Electronics. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS

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    • ABNT

      NICOLETT, Aparecido Sirley et al. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs. Solid-State Electronics, v. No 2000, n. 11, p. 1961-1969, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00166-0. Acesso em: 04 out. 2024.

    • APA

      Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2000). Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs. Solid-State Electronics, No 2000( 11), 1961-1969. doi:10.1016/s0038-1101(00)00166-0

    • NLM

      Nicolett AS, Martino JA, Simoen E, Claeys C. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs [Internet]. Solid-State Electronics. 2000 ; No 2000( 11): 1961-1969.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(00)00166-0

    • Vancouver

      Nicolett AS, Martino JA, Simoen E, Claeys C. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs [Internet]. Solid-State Electronics. 2000 ; No 2000( 11): 1961-1969.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(00)00166-0

  • Artigo de periodico

    Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects (2000)

    Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis

    Source: Solid-State Electronics. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS

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    • ABNT

      PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, v. 44, n. 6, p. 917-922, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00032-0. Acesso em: 04 out. 2024.

    • APA

      Pavanello, M. A., Martino, J. A., & Flandre, D. (2000). Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, 44( 6), 917-922. doi:10.1016/s0038-1101(00)00032-0

    • NLM

      Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0

    • Vancouver

      Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0

  • Artigo de periodico

    Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect (2000)

    Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor

    Source: Solid-State Electronics. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS

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    • ABNT

      NICOLETT, Aparecido Sirley et al. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect. Solid-State Electronics, v. 44, n. 4, p. 677-684, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(99)00293-2. Acesso em: 04 out. 2024.

    • APA

      Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2000). Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect. Solid-State Electronics, 44( 4), 677-684. doi:10.1016/s0038-1101(99)00293-2

    • NLM

      Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect [Internet]. Solid-State Electronics. 2000 ; 44( 4): 677-684.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(99)00293-2

    • Vancouver

      Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect [Internet]. Solid-State Electronics. 2000 ; 44( 4): 677-684.[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(99)00293-2

  • Artigo de periodico

    Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction (1999)

    Sonnenberg, Victor ; Martino, João Antonio

    Source: Solid-State Electronics. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS MOS

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    • ABNT

      SONNENBERG, Victor e MARTINO, João Antonio. Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction. Solid-State Electronics, 1999Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(99)00191-4. Acesso em: 04 out. 2024.

    • APA

      Sonnenberg, V., & Martino, J. A. (1999). Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction. Solid-State Electronics. doi:10.1016/s0038-1101(99)00191-4

    • NLM

      Sonnenberg V, Martino JA. Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction [Internet]. Solid-State Electronics. 1999 ;[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(99)00191-4

    • Vancouver

      Sonnenberg V, Martino JA. Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction [Internet]. Solid-State Electronics. 1999 ;[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(99)00191-4

  • Artigo de periodico

    Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's (1999)

    Pavanello, Marcelo Antonio ; Martino, João Antonio

    Source: Solid-State Electronics. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS MOS

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    • ABNT

      PAVANELLO, Marcelo Antonio e MARTINO, João Antonio. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's. Solid-State Electronics, 1999Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(99)00178-1. Acesso em: 04 out. 2024.

    • APA

      Pavanello, M. A., & Martino, J. A. (1999). Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's. Solid-State Electronics. doi:10.1016/s0038-1101(99)00178-1

    • NLM

      Pavanello MA, Martino JA. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's [Internet]. Solid-State Electronics. 1999 ;[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(99)00178-1

    • Vancouver

      Pavanello MA, Martino JA. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's [Internet]. Solid-State Electronics. 1999 ;[citado 2024 out. 04 ] Available from: https://doi.org/10.1016/s0038-1101(99)00178-1
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