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Artigo de periodico
A FAST hardware decoder optimized for template features to obtain order book Data in low latency (2023)
Oliveira, Caio C. S ; Bonato, Vanderlei
Source: Journal of Signal Processing Systems. Unidades: ICMC, EESC
Subjects: HARDWARE, ANÁLISE DE DADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
OLIVEIRA, Caio C. S e BONATO, Vanderlei. A FAST hardware decoder optimized for template features to obtain order book Data in low latency. Journal of Signal Processing Systems, v. 95, p. 559-567, 2023Tradução . . Disponível em: https://doi.org/10.1007/s11265-023-01850-2. Acesso em: 14 nov. 2024.
APA
Oliveira, C. C. S., & Bonato, V. (2023). A FAST hardware decoder optimized for template features to obtain order book Data in low latency. Journal of Signal Processing Systems, 95, 559-567. doi:10.1007/s11265-023-01850-2
NLM
Oliveira CCS, Bonato V. A FAST hardware decoder optimized for template features to obtain order book Data in low latency [Internet]. Journal of Signal Processing Systems. 2023 ; 95 559-567.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1007/s11265-023-01850-2
Vancouver
Oliveira CCS, Bonato V. A FAST hardware decoder optimized for template features to obtain order book Data in low latency [Internet]. Journal of Signal Processing Systems. 2023 ; 95 559-567.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1007/s11265-023-01850-2
Artigo de periodico
Order book mid-price movement inference by CatBoost classifier from convolutional feature maps (2022)
Bileki, Guilherme Augusto ; Barboza, Flavio Luiz de Moraes ; Silva, Luis Henrique Claudino ; Bonato, Vanderlei
Source: Applied Soft Computing. Unidade: ICMC
Subjects: APRENDIZADO COMPUTACIONAL, REDES NEURAIS, BOLSA DE VALORES, PREÇO DE AÇÕES
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BILEKI, Guilherme Augusto et al. Order book mid-price movement inference by CatBoost classifier from convolutional feature maps. Applied Soft Computing, v. 116, p. 1-13, 2022Tradução . . Disponível em: https://doi.org/10.1016/j.asoc.2021.108274. Acesso em: 14 nov. 2024.
APA
Bileki, G. A., Barboza, F. L. de M., Silva, L. H. C., & Bonato, V. (2022). Order book mid-price movement inference by CatBoost classifier from convolutional feature maps. Applied Soft Computing, 116, 1-13. doi:10.1016/j.asoc.2021.108274
NLM
Bileki GA, Barboza FL de M, Silva LHC, Bonato V. Order book mid-price movement inference by CatBoost classifier from convolutional feature maps [Internet]. Applied Soft Computing. 2022 ; 116 1-13.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1016/j.asoc.2021.108274
Vancouver
Bileki GA, Barboza FL de M, Silva LHC, Bonato V. Order book mid-price movement inference by CatBoost classifier from convolutional feature maps [Internet]. Applied Soft Computing. 2022 ; 116 1-13.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1016/j.asoc.2021.108274
Artigo de periodico
Class-specific early exit design methodology for convolutional neural networks (2021)
Bonato, Vanderlei ; Bouganis, Christos-Savvas
Source: Applied Soft Computing Journal. Unidade: ICMC
Subjects: HARDWARE, INFERÊNCIA, CONSUMO DE ENERGIA ELÉTRICA
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ABNT
BONATO, Vanderlei e BOUGANIS, Christos-Savvas. Class-specific early exit design methodology for convolutional neural networks. Applied Soft Computing Journal, v. 107, p. 1-12, 2021Tradução . . Disponível em: https://doi.org/10.1016/j.asoc.2021.107316. Acesso em: 14 nov. 2024.
APA
Bonato, V., & Bouganis, C. -S. (2021). Class-specific early exit design methodology for convolutional neural networks. Applied Soft Computing Journal, 107, 1-12. doi:10.1016/j.asoc.2021.107316
NLM
Bonato V, Bouganis C-S. Class-specific early exit design methodology for convolutional neural networks [Internet]. Applied Soft Computing Journal. 2021 ; 107 1-12.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1016/j.asoc.2021.107316
Vancouver
Bonato V, Bouganis C-S. Class-specific early exit design methodology for convolutional neural networks [Internet]. Applied Soft Computing Journal. 2021 ; 107 1-12.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1016/j.asoc.2021.107316
Artigo de periodico
Fast resource and timing aware design optimisation for high-level synthesis (2021)
Perina, André Bannwart ; Silitonga, Arthur ; Becker, Jürgen ; Bonato, Vanderlei
Source: IEEE Transactions on Computers. Unidade: ICMC
Subjects: HARDWARE, ANÁLISE DE DESEMPENHO
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PERINA, André Bannwart et al. Fast resource and timing aware design optimisation for high-level synthesis. IEEE Transactions on Computers, v. 70, n. 12, p. 2070-2082, 2021Tradução . . Disponível em: https://doi.org/10.1109/TC.2021.3112260. Acesso em: 14 nov. 2024.
APA
Perina, A. B., Silitonga, A., Becker, J., & Bonato, V. (2021). Fast resource and timing aware design optimisation for high-level synthesis. IEEE Transactions on Computers, 70( 12), 2070-2082. doi:10.1109/TC.2021.3112260
NLM
Perina AB, Silitonga A, Becker J, Bonato V. Fast resource and timing aware design optimisation for high-level synthesis [Internet]. IEEE Transactions on Computers. 2021 ; 70( 12): 2070-2082.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1109/TC.2021.3112260
Vancouver
Perina AB, Silitonga A, Becker J, Bonato V. Fast resource and timing aware design optimisation for high-level synthesis [Internet]. IEEE Transactions on Computers. 2021 ; 70( 12): 2070-2082.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1109/TC.2021.3112260
Artigo de periodico
Non-iterative SDC modulo scheduling for high-level synthesis (2021)
Rosa, Leandro de Souza ; Bouganis, Christos-Savvas ; Bonato, Vanderlei
Source: Microprocessors and Microsystems. Unidade: ICMC
Subjects: LAÇOS, HARDWARE, TEMPO
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ROSA, Leandro de Souza e BOUGANIS, Christos-Savvas e BONATO, Vanderlei. Non-iterative SDC modulo scheduling for high-level synthesis. Microprocessors and Microsystems, v. 86, p. 1-13, 2021Tradução . . Disponível em: https://doi.org/10.1016/j.micpro.2021.104334. Acesso em: 14 nov. 2024.
APA
Rosa, L. de S., Bouganis, C. -S., & Bonato, V. (2021). Non-iterative SDC modulo scheduling for high-level synthesis. Microprocessors and Microsystems, 86, 1-13. doi:10.1016/j.micpro.2021.104334
NLM
Rosa L de S, Bouganis C-S, Bonato V. Non-iterative SDC modulo scheduling for high-level synthesis [Internet]. Microprocessors and Microsystems. 2021 ; 86 1-13.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1016/j.micpro.2021.104334
Vancouver
Rosa L de S, Bouganis C-S, Bonato V. Non-iterative SDC modulo scheduling for high-level synthesis [Internet]. Microprocessors and Microsystems. 2021 ; 86 1-13.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1016/j.micpro.2021.104334
Artigo de periodico
A Faddeev systolic array for EKF-SLAM and its arithmetic data representation impact on FPGA (2018)
Rosa, Leandro de Souza; Dasu, Aravind; Diniz, Pedro C.; Bonato, Vanderlei
Source: Journal of Signal Processing Systems. Unidade: ICMC
Subjects: COMPUTAÇÃO RECONFIGURÁVEL, SISTEMAS EMBUTIDOS, ROBÓTICA, COMPUTAÇÃO EVOLUTIVA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ROSA, Leandro de Souza et al. A Faddeev systolic array for EKF-SLAM and its arithmetic data representation impact on FPGA. Journal of Signal Processing Systems, v. 90, n. 3, p. 357-369, 2018Tradução . . Disponível em: https://doi.org/10.1007/s11265-017-1243-9. Acesso em: 14 nov. 2024.
APA
Rosa, L. de S., Dasu, A., Diniz, P. C., & Bonato, V. (2018). A Faddeev systolic array for EKF-SLAM and its arithmetic data representation impact on FPGA. Journal of Signal Processing Systems, 90( 3), 357-369. doi:10.1007/s11265-017-1243-9
NLM
Rosa L de S, Dasu A, Diniz PC, Bonato V. A Faddeev systolic array for EKF-SLAM and its arithmetic data representation impact on FPGA [Internet]. Journal of Signal Processing Systems. 2018 ; 90( 3): 357-369.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1007/s11265-017-1243-9
Vancouver
Rosa L de S, Dasu A, Diniz PC, Bonato V. A Faddeev systolic array for EKF-SLAM and its arithmetic data representation impact on FPGA [Internet]. Journal of Signal Processing Systems. 2018 ; 90( 3): 357-369.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1007/s11265-017-1243-9
Artigo de periodico-carta/editorial
Special issue on applied reconfigurable computing [Editorial] (2017)
Bouganis, Christos-Savvas; Gorgon, Marek; Bonato, Vanderlei
Source: Microprocessors and Microsystems. Unidade: ICMC
Subjects: COMPUTAÇÃO RECONFIGURÁVEL, SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BOUGANIS, Christos-Savvas e GORGON, Marek e BONATO, Vanderlei. Special issue on applied reconfigurable computing [Editorial]. Microprocessors and Microsystems. Amsterdam: Instituto de Ciências Matemáticas e de Computação, Universidade de São Paulo. Disponível em: https://doi.org/10.1016/j.micpro.2017.05.010. Acesso em: 14 nov. 2024. , 2017
APA
Bouganis, C. -S., Gorgon, M., & Bonato, V. (2017). Special issue on applied reconfigurable computing [Editorial]. Microprocessors and Microsystems. Amsterdam: Instituto de Ciências Matemáticas e de Computação, Universidade de São Paulo. doi:10.1016/j.micpro.2017.05.010
NLM
Bouganis C-S, Gorgon M, Bonato V. Special issue on applied reconfigurable computing [Editorial] [Internet]. Microprocessors and Microsystems. 2017 ; 52 1.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1016/j.micpro.2017.05.010
Vancouver
Bouganis C-S, Gorgon M, Bonato V. Special issue on applied reconfigurable computing [Editorial] [Internet]. Microprocessors and Microsystems. 2017 ; 52 1.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1016/j.micpro.2017.05.010
Artigo de periodico
Design and analysis of evolutionary bit-length optimization algorithms for floating to fixed-point conversion (2016)
Rosa, L. S; Delbem, Alexandre Cláudio Botazzo ; Toledo, Claudio Fabiano Motta ; Bonato, Vanderlei
Source: Applied Soft Computing. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ROSA, L. S et al. Design and analysis of evolutionary bit-length optimization algorithms for floating to fixed-point conversion. Applied Soft Computing, v. 49, p. 447-461, 2016Tradução . . Disponível em: https://doi.org/10.1016/j.asoc.2016.08.035. Acesso em: 14 nov. 2024.
APA
Rosa, L. S., Delbem, A. C. B., Toledo, C. F. M., & Bonato, V. (2016). Design and analysis of evolutionary bit-length optimization algorithms for floating to fixed-point conversion. Applied Soft Computing, 49, 447-461. doi:10.1016/j.asoc.2016.08.035
NLM
Rosa LS, Delbem ACB, Toledo CFM, Bonato V. Design and analysis of evolutionary bit-length optimization algorithms for floating to fixed-point conversion [Internet]. Applied Soft Computing. 2016 ; 49 447-461.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1016/j.asoc.2016.08.035
Vancouver
Rosa LS, Delbem ACB, Toledo CFM, Bonato V. Design and analysis of evolutionary bit-length optimization algorithms for floating to fixed-point conversion [Internet]. Applied Soft Computing. 2016 ; 49 447-461.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1016/j.asoc.2016.08.035
Artigo de periodico
Accelerating floating-point to fixed-point data type conversion with evolutionary algorithms (2015)
Rosa, Leandro de Souza; Toledo, Claudio Fabiano Motta ; Bonato, Vanderlei
Source: Electronics Letters. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ROSA, Leandro de Souza e TOLEDO, Claudio Fabiano Motta e BONATO, Vanderlei. Accelerating floating-point to fixed-point data type conversion with evolutionary algorithms. Electronics Letters, v. Fe 2015, n. 3, p. 244-246, 2015Tradução . . Disponível em: https://doi.org/10.1049/el.2014.3791. Acesso em: 14 nov. 2024.
APA
Rosa, L. de S., Toledo, C. F. M., & Bonato, V. (2015). Accelerating floating-point to fixed-point data type conversion with evolutionary algorithms. Electronics Letters, Fe 2015( 3), 244-246. doi:10.1049/el.2014.3791
NLM
Rosa L de S, Toledo CFM, Bonato V. Accelerating floating-point to fixed-point data type conversion with evolutionary algorithms [Internet]. Electronics Letters. 2015 ; Fe 2015( 3): 244-246.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1049/el.2014.3791
Vancouver
Rosa L de S, Toledo CFM, Bonato V. Accelerating floating-point to fixed-point data type conversion with evolutionary algorithms [Internet]. Electronics Letters. 2015 ; Fe 2015( 3): 244-246.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1049/el.2014.3791
Trabalho de evento-anais periodico
LALPC: exploiting parallelism from FPGAS using C language (2015)
Porto, Lucas F.; Fernandes, Marcio M.; Bonato, Vanderlei ; Menotti, Ricardo
Source: Journal of Physics: Conference Series. Conference titles: Brazilian Symposium on High Performance Computational Systems - WSCAD 2014. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PORTO, Lucas F. et al. LALPC: exploiting parallelism from FPGAS using C language. Journal of Physics: Conference Series. Bristol: Institute of Physics - IOP. Disponível em: https://doi.org/10.1088/1742-6596/649/1/012001. Acesso em: 14 nov. 2024. , 2015
APA
Porto, L. F., Fernandes, M. M., Bonato, V., & Menotti, R. (2015). LALPC: exploiting parallelism from FPGAS using C language. Journal of Physics: Conference Series. Bristol: Institute of Physics - IOP. doi:10.1088/1742-6596/649/1/012001
NLM
Porto LF, Fernandes MM, Bonato V, Menotti R. LALPC: exploiting parallelism from FPGAS using C language [Internet]. Journal of Physics: Conference Series. 2015 ; 649 012001-1 - 012001-14.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1088/1742-6596/649/1/012001
Vancouver
Porto LF, Fernandes MM, Bonato V, Menotti R. LALPC: exploiting parallelism from FPGAS using C language [Internet]. Journal of Physics: Conference Series. 2015 ; 649 012001-1 - 012001-14.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1088/1742-6596/649/1/012001
Artigo de periodico
A Mersenne twister hardware implementation for the Monte Carlo localization algorithm (2013)
Bonato, Vanderlei ; Mazzotti, Bruno F; Fernandes, Marcio Merino; Marques, Eduardo
Source: Journal of Signal Processing Systems. Unidade: ICMC
Subjects: ARQUITETURA E ORGANIZAÇÃO DE COMPUTADORES, SISTEMAS EMBUTIDOS, ROBÓTICA, COMPUTAÇÃO EVOLUTIVA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BONATO, Vanderlei et al. A Mersenne twister hardware implementation for the Monte Carlo localization algorithm. Journal of Signal Processing Systems, v. 70, n. 1, p. 75-85, 2013Tradução . . Disponível em: https://doi.org/10.1007/s11265-012-0661-y. Acesso em: 14 nov. 2024.
APA
Bonato, V., Mazzotti, B. F., Fernandes, M. M., & Marques, E. (2013). A Mersenne twister hardware implementation for the Monte Carlo localization algorithm. Journal of Signal Processing Systems, 70( 1), 75-85. doi:10.1007/s11265-012-0661-y
NLM
Bonato V, Mazzotti BF, Fernandes MM, Marques E. A Mersenne twister hardware implementation for the Monte Carlo localization algorithm [Internet]. Journal of Signal Processing Systems. 2013 ; 70( 1): 75-85.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1007/s11265-012-0661-y
Vancouver
Bonato V, Mazzotti BF, Fernandes MM, Marques E. A Mersenne twister hardware implementation for the Monte Carlo localization algorithm [Internet]. Journal of Signal Processing Systems. 2013 ; 70( 1): 75-85.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1007/s11265-012-0661-y

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