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Filtros : "Indexado no INSPEC" "CIRCUITOS INTEGRADOS" "EP" Removidos: "Universidade Federal de Santa Catarina (UFSC)" "FM-MFT" "SANTOS, EDUARDO TOLEDO" "Argentina" Limpar

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  • Artigo de periodico

    Study of the drain leakage current behavior in graded-channel SOI nMOSFETs operating at high temperatures (2004)

    Bellodi, Marcello; Martino, João Antonio

    Source: Journal Integrated Circuits and Systems. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS

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    • ABNT

      BELLODI, Marcello e MARTINO, João Antonio. Study of the drain leakage current behavior in graded-channel SOI nMOSFETs operating at high temperatures. Journal Integrated Circuits and Systems, v. 1, n. 2, p. 31-35, 2004Tradução . . Disponível em: https://doi.org/10.29292/jics.v1i2.261. Acesso em: 09 out. 2024.

    • APA

      Bellodi, M., & Martino, J. A. (2004). Study of the drain leakage current behavior in graded-channel SOI nMOSFETs operating at high temperatures. Journal Integrated Circuits and Systems, 1( 2), 31-35. doi:10.29292/jics.v1i2.261

    • NLM

      Bellodi M, Martino JA. Study of the drain leakage current behavior in graded-channel SOI nMOSFETs operating at high temperatures [Internet]. Journal Integrated Circuits and Systems. 2004 ;1( 2): 31-35.[citado 2024 out. 09 ] Available from: https://doi.org/10.29292/jics.v1i2.261

    • Vancouver

      Bellodi M, Martino JA. Study of the drain leakage current behavior in graded-channel SOI nMOSFETs operating at high temperatures [Internet]. Journal Integrated Circuits and Systems. 2004 ;1( 2): 31-35.[citado 2024 out. 09 ] Available from: https://doi.org/10.29292/jics.v1i2.261

  • Artigo de periodico

    Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures (2001)

    Bellodi, Marcello; Martino, João Antonio

    Source: Solid-State Electronics. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS

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    • ABNT

      BELLODI, Marcello e MARTINO, João Antonio. Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures. Solid-State Electronics, v. 45, n. 5, p. 683-688, 2001Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(01)00099-5. Acesso em: 09 out. 2024.

    • APA

      Bellodi, M., & Martino, J. A. (2001). Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures. Solid-State Electronics, 45( 5), 683-688. doi:10.1016/s0038-1101(01)00099-5

    • NLM

      Bellodi M, Martino JA. Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures [Internet]. Solid-State Electronics. 2001 ; 45( 5): 683-688.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0038-1101(01)00099-5

    • Vancouver

      Bellodi M, Martino JA. Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures [Internet]. Solid-State Electronics. 2001 ; 45( 5): 683-688.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0038-1101(01)00099-5

  • Artigo de periodico

    Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs (2000)

    Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor

    Source: Solid-State Electronics. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS

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    • ABNT

      NICOLETT, Aparecido Sirley et al. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs. Solid-State Electronics, v. No 2000, n. 11, p. 1961-1969, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00166-0. Acesso em: 09 out. 2024.

    • APA

      Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2000). Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs. Solid-State Electronics, No 2000( 11), 1961-1969. doi:10.1016/s0038-1101(00)00166-0

    • NLM

      Nicolett AS, Martino JA, Simoen E, Claeys C. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs [Internet]. Solid-State Electronics. 2000 ; No 2000( 11): 1961-1969.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0038-1101(00)00166-0

    • Vancouver

      Nicolett AS, Martino JA, Simoen E, Claeys C. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs [Internet]. Solid-State Electronics. 2000 ; No 2000( 11): 1961-1969.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0038-1101(00)00166-0

  • Artigo de periodico

    Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects (2000)

    Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis

    Source: Solid-State Electronics. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS

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    • ABNT

      PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, v. 44, n. 6, p. 917-922, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00032-0. Acesso em: 09 out. 2024.

    • APA

      Pavanello, M. A., Martino, J. A., & Flandre, D. (2000). Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, 44( 6), 917-922. doi:10.1016/s0038-1101(00)00032-0

    • NLM

      Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0

    • Vancouver

      Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0

  • Artigo de periodico

    Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect (2000)

    Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor

    Source: Solid-State Electronics. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS

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    • ABNT

      NICOLETT, Aparecido Sirley et al. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect. Solid-State Electronics, v. 44, n. 4, p. 677-684, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(99)00293-2. Acesso em: 09 out. 2024.

    • APA

      Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2000). Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect. Solid-State Electronics, 44( 4), 677-684. doi:10.1016/s0038-1101(99)00293-2

    • NLM

      Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect [Internet]. Solid-State Electronics. 2000 ; 44( 4): 677-684.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0038-1101(99)00293-2

    • Vancouver

      Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect [Internet]. Solid-State Electronics. 2000 ; 44( 4): 677-684.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0038-1101(99)00293-2

  • Artigo de periodico

    Anisotropic reactive ion etching in silicon, using a graphite electrode (1998)

    Mansano, Ronaldo Domingues ; Verdonck, Patrick Bernard; Maciel, Homero Santiago

    Source: Sensors and Actuators A. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS

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    • ABNT

      MANSANO, Ronaldo Domingues e VERDONCK, Patrick Bernard e MACIEL, Homero Santiago. Anisotropic reactive ion etching in silicon, using a graphite electrode. Sensors and Actuators A, v. 65, n. 2-3, p. 180-186, 1998Tradução . . Disponível em: https://doi.org/10.1016/s0924-4247(97)01681-6. Acesso em: 09 out. 2024.

    • APA

      Mansano, R. D., Verdonck, P. B., & Maciel, H. S. (1998). Anisotropic reactive ion etching in silicon, using a graphite electrode. Sensors and Actuators A, 65( 2-3), 180-186. doi:10.1016/s0924-4247(97)01681-6

    • NLM

      Mansano RD, Verdonck PB, Maciel HS. Anisotropic reactive ion etching in silicon, using a graphite electrode [Internet]. Sensors and Actuators A. 1998 ; 65( 2-3): 180-186.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0924-4247(97)01681-6

    • Vancouver

      Mansano RD, Verdonck PB, Maciel HS. Anisotropic reactive ion etching in silicon, using a graphite electrode [Internet]. Sensors and Actuators A. 1998 ; 65( 2-3): 180-186.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0924-4247(97)01681-6

  • Artigo de periodico

    A simple technique to reduce the influence of the series resistance on the BULK and SOI MOSFET parameter extraction (1997)

    Nicolett, Aparecido Sirley; Martino, João Antonio

    Source: Journal of Solid-State Devices and Circuits. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS

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    • ABNT

      NICOLETT, Aparecido Sirley e MARTINO, João Antonio. A simple technique to reduce the influence of the series resistance on the BULK and SOI MOSFET parameter extraction. Journal of Solid-State Devices and Circuits, v. 5, n. 1, p. 5-8, 1997Tradução . . Acesso em: 09 out. 2024.

    • APA

      Nicolett, A. S., & Martino, J. A. (1997). A simple technique to reduce the influence of the series resistance on the BULK and SOI MOSFET parameter extraction. Journal of Solid-State Devices and Circuits, 5( 1), 5-8.

    • NLM

      Nicolett AS, Martino JA. A simple technique to reduce the influence of the series resistance on the BULK and SOI MOSFET parameter extraction. Journal of Solid-State Devices and Circuits. 1997 ;5( 1): 5-8.[citado 2024 out. 09 ]

    • Vancouver

      Nicolett AS, Martino JA. A simple technique to reduce the influence of the series resistance on the BULK and SOI MOSFET parameter extraction. Journal of Solid-State Devices and Circuits. 1997 ;5( 1): 5-8.[citado 2024 out. 09 ]

  • Artigo de periodico

    Mechanisms of surface roughness induced in silicon by fluorine containing plasmas (1997)

    Mansano, Ronaldo Domingues ; Verdonck, Patrick Bernard; Maciel, Homero Santiago

    Source: Vaccum. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS

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    • ABNT

      MANSANO, Ronaldo Domingues e VERDONCK, Patrick Bernard e MACIEL, Homero Santiago. Mechanisms of surface roughness induced in silicon by fluorine containing plasmas. Vaccum, v. 48, n. 7-9, p. 677-679, 1997Tradução . . Disponível em: https://doi.org/10.1016/s0042-207x(97)00067-5. Acesso em: 09 out. 2024.

    • APA

      Mansano, R. D., Verdonck, P. B., & Maciel, H. S. (1997). Mechanisms of surface roughness induced in silicon by fluorine containing plasmas. Vaccum, 48( 7-9), 677-679. doi:10.1016/s0042-207x(97)00067-5

    • NLM

      Mansano RD, Verdonck PB, Maciel HS. Mechanisms of surface roughness induced in silicon by fluorine containing plasmas [Internet]. Vaccum. 1997 ; 48( 7-9): 677-679.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0042-207x(97)00067-5

    • Vancouver

      Mansano RD, Verdonck PB, Maciel HS. Mechanisms of surface roughness induced in silicon by fluorine containing plasmas [Internet]. Vaccum. 1997 ; 48( 7-9): 677-679.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0042-207x(97)00067-5

  • Artigo de periodico

    Reactive ion etching and plasma etching of tungsten (1993)

    Verdonck, Patrick Bernard; Brasseur, G.; Swart, J.

    Source: Microelectronic Engineering. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS

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    • ABNT

      VERDONCK, Patrick Bernard e BRASSEUR, G. e SWART, J. Reactive ion etching and plasma etching of tungsten. Microelectronic Engineering, v. 21, p. 329-332, 1993Tradução . . Disponível em: https://doi.org/10.1016/0167-9317(93)90084-i. Acesso em: 09 out. 2024.

    • APA

      Verdonck, P. B., Brasseur, G., & Swart, J. (1993). Reactive ion etching and plasma etching of tungsten. Microelectronic Engineering, 21, 329-332. doi:10.1016/0167-9317(93)90084-i

    • NLM

      Verdonck PB, Brasseur G, Swart J. Reactive ion etching and plasma etching of tungsten [Internet]. Microelectronic Engineering. 1993 ; 21 329-332.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/0167-9317(93)90084-i

    • Vancouver

      Verdonck PB, Brasseur G, Swart J. Reactive ion etching and plasma etching of tungsten [Internet]. Microelectronic Engineering. 1993 ; 21 329-332.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/0167-9317(93)90084-i

  • Artigo de periodico

    Laser enhanced polymer etching in different ambients (1989)

    Verdonck, Patrick Bernard; Brasseur, G.; Coopmans, F.

    Source: Microelectronic Engineering. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS

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    • ABNT

      VERDONCK, Patrick Bernard e BRASSEUR, G. e COOPMANS, F. Laser enhanced polymer etching in different ambients. Microelectronic Engineering, v. 9, p. 507-510, 1989Tradução . . Disponível em: https://doi.org/10.1016/0167-9317(89)90111-1. Acesso em: 09 out. 2024.

    • APA

      Verdonck, P. B., Brasseur, G., & Coopmans, F. (1989). Laser enhanced polymer etching in different ambients. Microelectronic Engineering, 9, 507-510. doi:10.1016/0167-9317(89)90111-1

    • NLM

      Verdonck PB, Brasseur G, Coopmans F. Laser enhanced polymer etching in different ambients [Internet]. Microelectronic Engineering. 1989 ; 9 507-510.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/0167-9317(89)90111-1

    • Vancouver

      Verdonck PB, Brasseur G, Coopmans F. Laser enhanced polymer etching in different ambients [Internet]. Microelectronic Engineering. 1989 ; 9 507-510.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/0167-9317(89)90111-1
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