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Trabalho de evento
Low frequency noise assessment in advanced UTBOX SOI n-channel MOSFETs (2013)
Martino, João Antonio ; Strobel, V.; Cretu, B.; Santos, Sara Dereste dos; Simoen, Eddy ; Routure, J.-M.; Carin, R.; Aoulaiche, Marc; Claeys, Cor
Source: EUROSOI 2013. Conference titles: European Workshop on Silicon on Insulator Technology, Devices and Circuits. Unidade: EP
Assunto: MICROELETRÔNICA (CONGRESSOS)
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ABNT
MARTINO, João Antonio et al. Low frequency noise assessment in advanced UTBOX SOI n-channel MOSFETs. 2013, Anais.. Paris: Institut Superieur d'Électronique, 2013. . Acesso em: 03 nov. 2024.
APA
Martino, J. A., Strobel, V., Cretu, B., Santos, S. D. dos, Simoen, E., Routure, J. -M., et al. (2013). Low frequency noise assessment in advanced UTBOX SOI n-channel MOSFETs. In EUROSOI 2013. Paris: Institut Superieur d'Électronique.
NLM
Martino JA, Strobel V, Cretu B, Santos SD dos, Simoen E, Routure J-M, Carin R, Aoulaiche M, Claeys C. Low frequency noise assessment in advanced UTBOX SOI n-channel MOSFETs. EUROSOI 2013. 2013 ;[citado 2024 nov. 03 ]
Vancouver
Martino JA, Strobel V, Cretu B, Santos SD dos, Simoen E, Routure J-M, Carin R, Aoulaiche M, Claeys C. Low frequency noise assessment in advanced UTBOX SOI n-channel MOSFETs. EUROSOI 2013. 2013 ;[citado 2024 nov. 03 ]
Trabalho de evento
Influence of interface trap density on vertical NW-TFETs with different source composition (2013)
Martino, João Antonio ; Souza, Felipe Neves; Agopian, Paula Ghedini Der ; Rooyackers, Rita; Vandooren, A.; Simoen, Eddy ; Claeys, Cor
Source: EUROSOI 2013. Conference titles: European Workshop on Silicon on Insulator Technology, Devices and Circuits. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
MARTINO, João Antonio et al. Influence of interface trap density on vertical NW-TFETs with different source composition. 2013, Anais.. Paris: Institut Superieur d'Électronique, 2013. . Acesso em: 03 nov. 2024.
APA
Martino, J. A., Souza, F. N., Agopian, P. G. D., Rooyackers, R., Vandooren, A., Simoen, E., & Claeys, C. (2013). Influence of interface trap density on vertical NW-TFETs with different source composition. In EUROSOI 2013. Paris: Institut Superieur d'Électronique.
NLM
Martino JA, Souza FN, Agopian PGD, Rooyackers R, Vandooren A, Simoen E, Claeys C. Influence of interface trap density on vertical NW-TFETs with different source composition. EUROSOI 2013. 2013 ;[citado 2024 nov. 03 ]
Vancouver
Martino JA, Souza FN, Agopian PGD, Rooyackers R, Vandooren A, Simoen E, Claeys C. Influence of interface trap density on vertical NW-TFETs with different source composition. EUROSOI 2013. 2013 ;[citado 2024 nov. 03 ]
Trabalho de evento
Low-frequency noise for different gate dielectrics on state-of-the-art UTBOX SOI nMOSFETs (2013)
Martino, João Antonio ; Santos, Sara Dereste dos; Simoen, Eddy ; Strobe, V.; Cretu, B.; Routoure, J.-M.; Carin, R.; Aoulaiche, Marc; Veloso, Anabela; Claeys, Cor
Source: EUROSOI 2013. Conference titles: European Workshop on Silicon on Insulator Technology, Devices and Circuits. Unidade: EP
Assunto: MICROELETRÔNICA (CONGRESSOS)
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ABNT
MARTINO, João Antonio et al. Low-frequency noise for different gate dielectrics on state-of-the-art UTBOX SOI nMOSFETs. 2013, Anais.. Paris: Institut Superieur d'Électronique, 2013. . Acesso em: 03 nov. 2024.
APA
Martino, J. A., Santos, S. D. dos, Simoen, E., Strobe, V., Cretu, B., Routoure, J. -M., et al. (2013). Low-frequency noise for different gate dielectrics on state-of-the-art UTBOX SOI nMOSFETs. In EUROSOI 2013. Paris: Institut Superieur d'Électronique.
NLM
Martino JA, Santos SD dos, Simoen E, Strobe V, Cretu B, Routoure J-M, Carin R, Aoulaiche M, Veloso A, Claeys C. Low-frequency noise for different gate dielectrics on state-of-the-art UTBOX SOI nMOSFETs. EUROSOI 2013. 2013 ;[citado 2024 nov. 03 ]
Vancouver
Martino JA, Santos SD dos, Simoen E, Strobe V, Cretu B, Routoure J-M, Carin R, Aoulaiche M, Veloso A, Claeys C. Low-frequency noise for different gate dielectrics on state-of-the-art UTBOX SOI nMOSFETs. EUROSOI 2013. 2013 ;[citado 2024 nov. 03 ]
Trabalho de evento
Experimental comparison between tensile and compressive uniaxially stressed MuGFETs under X-ray radiation (2013)
Martino, João Antonio ; Agopian, Paula Ghedini Der ; Peruzzi, V. V.; Gimenez, Salvador Pinillos ; Silveira, M. A. G.; Simoen, Eddy ; Claeys, Cor
Source: EUROSOI 2013. Conference titles: European Workshop on Silicon on Insulator Technology, Devices and Circuits. Unidade: EP
Assunto: MICROELETRÔNICA (CONGRESSOS)
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ABNT
MARTINO, João Antonio et al. Experimental comparison between tensile and compressive uniaxially stressed MuGFETs under X-ray radiation. 2013, Anais.. Paris: Institut Superieur d'Électronique, 2013. . Acesso em: 03 nov. 2024.
APA
Martino, J. A., Agopian, P. G. D., Peruzzi, V. V., Gimenez, S. P., Silveira, M. A. G., Simoen, E., & Claeys, C. (2013). Experimental comparison between tensile and compressive uniaxially stressed MuGFETs under X-ray radiation. In EUROSOI 2013. Paris: Institut Superieur d'Électronique.
NLM
Martino JA, Agopian PGD, Peruzzi VV, Gimenez SP, Silveira MAG, Simoen E, Claeys C. Experimental comparison between tensile and compressive uniaxially stressed MuGFETs under X-ray radiation. EUROSOI 2013. 2013 ;[citado 2024 nov. 03 ]
Vancouver
Martino JA, Agopian PGD, Peruzzi VV, Gimenez SP, Silveira MAG, Simoen E, Claeys C. Experimental comparison between tensile and compressive uniaxially stressed MuGFETs under X-ray radiation. EUROSOI 2013. 2013 ;[citado 2024 nov. 03 ]
Trabalho de evento
Improvement of Retention Time Using Pulsed Back Gate Bias on UTBOX SOI Memory Cell (2013)
Martino, João Antonio ; Sasaki, Katia Regina Akemi; Nissimoff, Albert; Almeida, Luciano Mendes; Aoulaiche, Marc; Simoen, Eddy ; Claeys, Cor
Source: EUROSOI 2013. Conference titles: European Workshop on Silicon on Insulator Technology, Devices and Circuits. Unidade: EP
Assunto: MICROELETRÔNICA (CONGRESSOS)
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ABNT
MARTINO, João Antonio et al. Improvement of Retention Time Using Pulsed Back Gate Bias on UTBOX SOI Memory Cell. 2013, Anais.. Paris: Institut Superieur d'Électronique, 2013. . Acesso em: 03 nov. 2024.
APA
Martino, J. A., Sasaki, K. R. A., Nissimoff, A., Almeida, L. M., Aoulaiche, M., Simoen, E., & Claeys, C. (2013). Improvement of Retention Time Using Pulsed Back Gate Bias on UTBOX SOI Memory Cell. In EUROSOI 2013. Paris: Institut Superieur d'Électronique.
NLM
Martino JA, Sasaki KRA, Nissimoff A, Almeida LM, Aoulaiche M, Simoen E, Claeys C. Improvement of Retention Time Using Pulsed Back Gate Bias on UTBOX SOI Memory Cell. EUROSOI 2013. 2013 ;[citado 2024 nov. 03 ]
Vancouver
Martino JA, Sasaki KRA, Nissimoff A, Almeida LM, Aoulaiche M, Simoen E, Claeys C. Improvement of Retention Time Using Pulsed Back Gate Bias on UTBOX SOI Memory Cell. EUROSOI 2013. 2013 ;[citado 2024 nov. 03 ]
Trabalho de evento
Experimental and Simulation of 1T-DRAM Trend with the Gate Length on UTBOX Devices (2013)
Martino, João Antonio ; Nicoletti, Talitha; Sasaki, Katia Regina Akemi; Aoulaiche, Marc; Simoen, Eddy ; Claeys, Cor
Source: EUROSOI 2013. Conference titles: European Workshop on Silicon on Insulator Technology, Devices and Circuits. Unidade: EP
Assunto: MICROELETRÔNICA (CONGRESSOS)
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ABNT
MARTINO, João Antonio et al. Experimental and Simulation of 1T-DRAM Trend with the Gate Length on UTBOX Devices. 2013, Anais.. Paris: Institut Superieur d'Électronique, 2013. . Acesso em: 03 nov. 2024.
APA
Martino, J. A., Nicoletti, T., Sasaki, K. R. A., Aoulaiche, M., Simoen, E., & Claeys, C. (2013). Experimental and Simulation of 1T-DRAM Trend with the Gate Length on UTBOX Devices. In EUROSOI 2013. Paris: Institut Superieur d'Électronique.
NLM
Martino JA, Nicoletti T, Sasaki KRA, Aoulaiche M, Simoen E, Claeys C. Experimental and Simulation of 1T-DRAM Trend with the Gate Length on UTBOX Devices. EUROSOI 2013. 2013 ;[citado 2024 nov. 03 ]
Vancouver
Martino JA, Nicoletti T, Sasaki KRA, Aoulaiche M, Simoen E, Claeys C. Experimental and Simulation of 1T-DRAM Trend with the Gate Length on UTBOX Devices. EUROSOI 2013. 2013 ;[citado 2024 nov. 03 ]
Trabalho de evento-anais periodico
Study of the Main Digital and Analog Parameters of Underlapped MuGFETs (2012)
Martino, João Antonio ; Santos, Sara Dereste dos; Nicoletti, Talitha; Aoulaiche, Marc; Simoen, Eddy ; Claeys, Cor
Source: VIII Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits. Conference titles: European Workshop on Silicon on Insulator Technology, Devices and Circuits. Unidade: EP
Assunto: MICROELETRÔNICA (CONGRESSOS)
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ABNT
MARTINO, João Antonio et al. Study of the Main Digital and Analog Parameters of Underlapped MuGFETs. VIII Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits. S.l: Institut d'Électronique. . Acesso em: 03 nov. 2024. , 2012
APA
Martino, J. A., Santos, S. D. dos, Nicoletti, T., Aoulaiche, M., Simoen, E., & Claeys, C. (2012). Study of the Main Digital and Analog Parameters of Underlapped MuGFETs. VIII Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits. S.l: Institut d'Électronique.
NLM
Martino JA, Santos SD dos, Nicoletti T, Aoulaiche M, Simoen E, Claeys C. Study of the Main Digital and Analog Parameters of Underlapped MuGFETs. VIII Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits. 2012 ;[citado 2024 nov. 03 ]
Vancouver
Martino JA, Santos SD dos, Nicoletti T, Aoulaiche M, Simoen E, Claeys C. Study of the Main Digital and Analog Parameters of Underlapped MuGFETs. VIII Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits. 2012 ;[citado 2024 nov. 03 ]
Artigo de periodico
Impact of SEG on uniaxially strained MuGFET performance (2011)
Agopian, Paula Ghedini Der ; Pacheco, Vinicius Heltai; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Solid-state electronics. Unidade: EP
Assunto: BAIXA TEMPERATURA
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ABNT
AGOPIAN, Paula Ghedini Der et al. Impact of SEG on uniaxially strained MuGFET performance. Solid-state electronics, v. 59, n. 1, p. 13-17, 2011Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2011.01.009. Acesso em: 03 nov. 2024.
APA
Agopian, P. G. D., Pacheco, V. H., Martino, J. A., Simoen, E., & Claeys, C. (2011). Impact of SEG on uniaxially strained MuGFET performance. Solid-state electronics, 59( 1), 13-17. doi:10.1016/j.sse.2011.01.009
NLM
Agopian PGD, Pacheco VH, Martino JA, Simoen E, Claeys C. Impact of SEG on uniaxially strained MuGFET performance [Internet]. Solid-state electronics. 2011 ; 59( 1): 13-17.[citado 2024 nov. 03 ] Available from: https://doi.org/10.1016/j.sse.2011.01.009
Vancouver
Agopian PGD, Pacheco VH, Martino JA, Simoen E, Claeys C. Impact of SEG on uniaxially strained MuGFET performance [Internet]. Solid-state electronics. 2011 ; 59( 1): 13-17.[citado 2024 nov. 03 ] Available from: https://doi.org/10.1016/j.sse.2011.01.009
Artigo de periodico
Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body (2002)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Mercha, A.; Rafi, J.M.; Simoen, Eddy ; Claeys, Cor ; Van Meer, H.; De Meyer, K.
Source: Journal de Physique IV. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
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ABNT
PAVANELLO, Marcelo Antonio et al. Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV, v. 12, n. 3, 2002Tradução . . Acesso em: 03 nov. 2024.
APA
Pavanello, M. A., Martino, J. A., Mercha, A., Rafi, J. M., Simoen, E., Claeys, C., et al. (2002). Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV, 12( 3).
NLM
Pavanello MA, Martino JA, Mercha A, Rafi JM, Simoen E, Claeys C, Van Meer H, De Meyer K. Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV. 2002 ;12( 3):[citado 2024 nov. 03 ]
Vancouver
Pavanello MA, Martino JA, Mercha A, Rafi JM, Simoen E, Claeys C, Van Meer H, De Meyer K. Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV. 2002 ;12( 3):[citado 2024 nov. 03 ]
Artigo de periodico
Back gate voltage and buried oxide thickness influences on the series resistence of fully depleted SOI MOSFETs at 77K (1998)
Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Journal de Physique IV. Unidade: EP
Assunto: ENERGIA ELÉTRICA
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ABNT
NICOLETT, Aparecido Sirley et al. Back gate voltage and buried oxide thickness influences on the series resistence of fully depleted SOI MOSFETs at 77K. Journal de Physique IV, v. 8, p. 25-28, 1998Tradução . . Disponível em: https://doi.org/10.1051/jp4:1998306. Acesso em: 03 nov. 2024.
APA
Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (1998). Back gate voltage and buried oxide thickness influences on the series resistence of fully depleted SOI MOSFETs at 77K. Journal de Physique IV, 8, 25-28. doi:10.1051/jp4:1998306
NLM
Nicolett AS, Martino JA, Simoen E, Claeys C. Back gate voltage and buried oxide thickness influences on the series resistence of fully depleted SOI MOSFETs at 77K [Internet]. Journal de Physique IV. 1998 ;8 25-28.[citado 2024 nov. 03 ] Available from: https://doi.org/10.1051/jp4:1998306
Vancouver
Nicolett AS, Martino JA, Simoen E, Claeys C. Back gate voltage and buried oxide thickness influences on the series resistence of fully depleted SOI MOSFETs at 77K [Internet]. Journal de Physique IV. 1998 ;8 25-28.[citado 2024 nov. 03 ] Available from: https://doi.org/10.1051/jp4:1998306
Artigo de periodico
Mobility degradation influence on the SOI MOSFET channel length extraction at 77K (1996)
Nicolett, Aparecido Sirley; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Journal de Physique IV Colloque 3, supplement au Journal de Physique III. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
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ABNT
NICOLETT, Aparecido Sirley et al. Mobility degradation influence on the SOI MOSFET channel length extraction at 77K. Journal de Physique IV Colloque 3, supplement au Journal de Physique III, v. 6, 1996Tradução . . Acesso em: 03 nov. 2024.
APA
Nicolett, A. S., Simoen, E., Claeys, C., & Martino, J. A. (1996). Mobility degradation influence on the SOI MOSFET channel length extraction at 77K. Journal de Physique IV Colloque 3, supplement au Journal de Physique III, 6.
NLM
Nicolett AS, Simoen E, Claeys C, Martino JA. Mobility degradation influence on the SOI MOSFET channel length extraction at 77K. Journal de Physique IV Colloque 3, supplement au Journal de Physique III. 1996 ;6[citado 2024 nov. 03 ]
Vancouver
Nicolett AS, Simoen E, Claeys C, Martino JA. Mobility degradation influence on the SOI MOSFET channel length extraction at 77K. Journal de Physique IV Colloque 3, supplement au Journal de Physique III. 1996 ;6[citado 2024 nov. 03 ]
Artigo de periodico
Parameter extraction of MOSFETs operated at low temperature (1996)
Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Journal de Physique IV Colloque 3, supplement au Journal de Physique III. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
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ABNT
SIMOEN, Eddy e CLAEYS, Cor e MARTINO, João Antonio. Parameter extraction of MOSFETs operated at low temperature. Journal de Physique IV Colloque 3, supplement au Journal de Physique III, v. 6, 1996Tradução . . Acesso em: 03 nov. 2024.
APA
Simoen, E., Claeys, C., & Martino, J. A. (1996). Parameter extraction of MOSFETs operated at low temperature. Journal de Physique IV Colloque 3, supplement au Journal de Physique III, 6.
NLM
Simoen E, Claeys C, Martino JA. Parameter extraction of MOSFETs operated at low temperature. Journal de Physique IV Colloque 3, supplement au Journal de Physique III. 1996 ;6[citado 2024 nov. 03 ]
Vancouver
Simoen E, Claeys C, Martino JA. Parameter extraction of MOSFETs operated at low temperature. Journal de Physique IV Colloque 3, supplement au Journal de Physique III. 1996 ;6[citado 2024 nov. 03 ]

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