Experimental and Simulation of 1T-DRAM Trend with the Gate Length on UTBOX Devices (2013)
- Authors:
- USP affiliated authors: MARTINO, JOAO ANTONIO - EP ; SASAKI, KATIA REGINA AKEMI - EP ; NICOLETTI, TALITHA - EP
- Unidade: EP
- Assunto: MICROELETRÔNICA (CONGRESSOS)
- Language: Inglês
- Imprenta:
- Publisher: Institut Superieur d'Électronique
- Publisher place: Paris
- Date published: 2013
- Source:
- Título do periódico: EUROSOI 2013
- Conference titles: European Workshop on Silicon on Insulator Technology, Devices and Circuits
-
ABNT
MARTINO, João Antonio et al. Experimental and Simulation of 1T-DRAM Trend with the Gate Length on UTBOX Devices. 2013, Anais.. Paris: Institut Superieur d'Électronique, 2013. . Acesso em: 30 set. 2024. -
APA
Martino, J. A., Nicoletti, T., Sasaki, K. R. A., Aoulaiche, M., Simoen, E., & Claeys, C. (2013). Experimental and Simulation of 1T-DRAM Trend with the Gate Length on UTBOX Devices. In EUROSOI 2013. Paris: Institut Superieur d'Électronique. -
NLM
Martino JA, Nicoletti T, Sasaki KRA, Aoulaiche M, Simoen E, Claeys C. Experimental and Simulation of 1T-DRAM Trend with the Gate Length on UTBOX Devices. EUROSOI 2013. 2013 ;[citado 2024 set. 30 ] -
Vancouver
Martino JA, Nicoletti T, Sasaki KRA, Aoulaiche M, Simoen E, Claeys C. Experimental and Simulation of 1T-DRAM Trend with the Gate Length on UTBOX Devices. EUROSOI 2013. 2013 ;[citado 2024 set. 30 ] - DIBL behavior of triple gate FinFETs with SEG on biaxial strained devices
- On the Variability of the Front-/Back-Channel LF Noise in UTBOX SOI nMOSFETs
- Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS
- Optimizing the front and back biases for the best sense margin and retention time in UTBOX FBRAM
- Enhanced dynamic threshold voltage UTBB SOI nMOSFETs
- Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View
- Impact of the extension region concentration on the UTBOX IT-FBRAM
- Propostas de melhorias de desempenho de célula de memória dinâmica utilizando um único transistor UTBOX SOI
- Estudo de transistores UTBOX SOI não auto-alinhados como célula de memória
- Improvement of Retention Time Using Pulsed Back Gate Bias on UTBOX SOI Memory Cell
How to cite
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas