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Artigo de periodico
Experimental study of MISHEMT from 450 K down to 200 K for analog applications (2023)
Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Fonte: Solid State Electronics. Unidade: EP
Assuntos: TRANSISTORES, CIRCUITOS ANALÓGICOS, SEMICONDUTORES
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ABNT
PERINA, Welder Fernandes et al. Experimental study of MISHEMT from 450 K down to 200 K for analog applications. Solid State Electronics, v. 208, p. 1-4, 2023Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108742. Acesso em: 31 out. 2024.
APA
Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). Experimental study of MISHEMT from 450 K down to 200 K for analog applications. Solid State Electronics, 208, 1-4. doi:10.1016/j.sse.2023.108742
NLM
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450 K down to 200 K for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 out. 31 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Vancouver
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450 K down to 200 K for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 out. 31 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Artigo de periodico
Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications (2023)
Silva, V C P; Martino, João Antonio ; Simoen, Eddy ; Veloso, Anabela; Agopian, Paula Ghedini Der
Fonte: Solid State Electronics. Unidade: EP
Assuntos: TRANSISTORES, TEMPERATURA, NANOTECNOLOGIA, CIRCUITOS ANALÓGICOS, CIRCUITOS DIGITAIS
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ABNT
SILVA, V C P et al. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications. Solid State Electronics, v. 208, p. 1-5, 2023Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108729. Acesso em: 31 out. 2024.
APA
Silva, V. C. P., Martino, J. A., Simoen, E., Veloso, A., & Agopian, P. G. D. (2023). Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications. Solid State Electronics, 208, 1-5. doi:10.1016/j.sse.2023.108729
NLM
Silva VCP, Martino JA, Simoen E, Veloso A, Agopian PGD. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications [Internet]. Solid State Electronics. 2023 ;208 1-5.[citado 2024 out. 31 ] Available from: https://doi.org/10.1016/j.sse.2023.108729
Vancouver
Silva VCP, Martino JA, Simoen E, Veloso A, Agopian PGD. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications [Internet]. Solid State Electronics. 2023 ;208 1-5.[citado 2024 out. 31 ] Available from: https://doi.org/10.1016/j.sse.2023.108729
Artigo de periodico
Experimental study of MISHEMT from 450k down to 200 k for analog applications (2023)
Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Fonte: Solid State Electronics. Unidade: EP
Assuntos: TRANSISTORES, CIRCUITOS ANALÓGICOS, TEMPERATURA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PERINA, Welder Fernandes et al. Experimental study of MISHEMT from 450k down to 200 k for analog applications. Solid State Electronics, v. 208, p. 1-4, 2023Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108742. Acesso em: 31 out. 2024.
APA
Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). Experimental study of MISHEMT from 450k down to 200 k for analog applications. Solid State Electronics, 208, 1-4. doi:10.1016/j.sse.2023.108742
NLM
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450k down to 200 k for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 out. 31 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Vancouver
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450k down to 200 k for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 out. 31 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Trabalho de evento
Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K (2023)
Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Fonte: SBMicro. Nome do evento: Symposium on Microelectronics Technology and Devices. Unidade: EP
Assuntos: TRANSISTORES, SEMICONDUTORES
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ABNT
PERINA, Welder Fernandes et al. Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K. 2023, Anais.. [Piscataway, N.J.]: IEEE, 2023. Disponível em: https://doi.org/10.1109/SBMicro60499.2023.10302604. Acesso em: 31 out. 2024.
APA
Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K. In SBMicro. [Piscataway, N.J.]: IEEE. doi:10.1109/SBMicro60499.2023.10302604
NLM
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K [Internet]. SBMicro. 2023 ;[citado 2024 out. 31 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302604
Vancouver
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K [Internet]. SBMicro. 2023 ;[citado 2024 out. 31 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302604
Artigo de periodico
MISHEMT intrinsic voltage gain under multiple channel output characteristics (2023)
Canales, Bruno Godoy; Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Fonte: Semiconductor Science and Technology. Unidade: EP
Assuntos: TRANSISTORES, SEMICONDUTORES
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ABNT
CANALES, Bruno Godoy et al. MISHEMT intrinsic voltage gain under multiple channel output characteristics. Semiconductor Science and Technology, v. 38, n. 11, p. 1-6, 2023Tradução . . Disponível em: https://doi.org/10.1088/1361-6641/acfa1f. Acesso em: 31 out. 2024.
APA
Canales, B. G., Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). MISHEMT intrinsic voltage gain under multiple channel output characteristics. Semiconductor Science and Technology, 38( 11), 1-6. doi:10.1088/1361-6641/acfa1f
NLM
Canales BG, Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. MISHEMT intrinsic voltage gain under multiple channel output characteristics [Internet]. Semiconductor Science and Technology. 2023 ; 38( 11): 1-6.[citado 2024 out. 31 ] Available from: https://doi.org/10.1088/1361-6641/acfa1f
Vancouver
Canales BG, Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. MISHEMT intrinsic voltage gain under multiple channel output characteristics [Internet]. Semiconductor Science and Technology. 2023 ; 38( 11): 1-6.[citado 2024 out. 31 ] Available from: https://doi.org/10.1088/1361-6641/acfa1f
Artigo de periodico
Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C (2022)
Sousa, Julia Cristina Soares; Perina, Welder F; Rangel, Roberto; Simoen, Eddy ; Veloso, Anabela; Martino, João Antonio ; Agopian, Paula Ghedini Der
Fonte: Solid State Electronics. Unidade: EP
Assuntos: NANOTECNOLOGIA, CIRCUITOS ANALÓGICOS, TRANSISTORES
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ABNT
SOUSA, Julia Cristina Soares et al. Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C. Solid State Electronics, v. 189, p. 1-9, 2022Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2022.108238. Acesso em: 31 out. 2024.
APA
Sousa, J. C. S., Perina, W. F., Rangel, R., Simoen, E., Veloso, A., Martino, J. A., & Agopian, P. G. D. (2022). Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C. Solid State Electronics, 189, 1-9. doi:10.1016/j.sse.2022.108238
NLM
Sousa JCS, Perina WF, Rangel R, Simoen E, Veloso A, Martino JA, Agopian PGD. Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C [Internet]. Solid State Electronics. 2022 ;189 1-9.[citado 2024 out. 31 ] Available from: https://doi.org/10.1016/j.sse.2022.108238
Vancouver
Sousa JCS, Perina WF, Rangel R, Simoen E, Veloso A, Martino JA, Agopian PGD. Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C [Internet]. Solid State Electronics. 2022 ;189 1-9.[citado 2024 out. 31 ] Available from: https://doi.org/10.1016/j.sse.2022.108238
Artigo de periodico
Performance perspective of gate-all-around double nanosheet CMOS beyond high-speed logic applications (2022)
Simoen, Eddy ; Coelho, Carlos Henrique Santos; Silva, Vanessa Cristina Pereira da; Martino, João Antonio ; Agopian, Paula Ghedini Der ; Oliveira, Alberto; Cretu, Bogdan; Veloso, Anabela
Fonte: Journal of Integrated Circuits and Systems. Unidades: EP, EESC
Assuntos: TRANSISTORES, NANOELETRÔNICA, TEMPERATURA
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ABNT
SIMOEN, Eddy et al. Performance perspective of gate-all-around double nanosheet CMOS beyond high-speed logic applications. Journal of Integrated Circuits and Systems, v. 17, n. 2, p. 1-9, 2022Tradução . . Disponível em: https://doi.org/10.29292/jics.v17i2.617. Acesso em: 31 out. 2024.
APA
Simoen, E., Coelho, C. H. S., Silva, V. C. P. da, Martino, J. A., Agopian, P. G. D., Oliveira, A., et al. (2022). Performance perspective of gate-all-around double nanosheet CMOS beyond high-speed logic applications. Journal of Integrated Circuits and Systems, 17( 2), 1-9. doi:10.29292/jics.v17i2.617
NLM
Simoen E, Coelho CHS, Silva VCP da, Martino JA, Agopian PGD, Oliveira A, Cretu B, Veloso A. Performance perspective of gate-all-around double nanosheet CMOS beyond high-speed logic applications [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-9.[citado 2024 out. 31 ] Available from: https://doi.org/10.29292/jics.v17i2.617
Vancouver
Simoen E, Coelho CHS, Silva VCP da, Martino JA, Agopian PGD, Oliveira A, Cretu B, Veloso A. Performance perspective of gate-all-around double nanosheet CMOS beyond high-speed logic applications [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-9.[citado 2024 out. 31 ] Available from: https://doi.org/10.29292/jics.v17i2.617
Artigo de periodico
Tunnel-FET evolution and applications for analog circuits (2022)
Agopian, Paula Ghedini Der ; Martino, João Antonio ; Simoen, Eddy ; Rooyackers, Rita ; Claeys, Cor
Fonte: Journal of Integrated Circuits and Systems. Unidade: EP
Assuntos: TRANSISTORES, SENSOR, CIRCUITOS ANALÓGICOS, CIRCUITOS DIGITAIS
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ABNT
AGOPIAN, Paula Ghedini Der et al. Tunnel-FET evolution and applications for analog circuits. Journal of Integrated Circuits and Systems, v. 17, n. 2, p. 1-7, 2022Tradução . . Disponível em: https://doi.org/10.29292/jics.v17i2.631. Acesso em: 31 out. 2024.
APA
Agopian, P. G. D., Martino, J. A., Simoen, E., Rooyackers, R., & Claeys, C. (2022). Tunnel-FET evolution and applications for analog circuits. Journal of Integrated Circuits and Systems, 17( 2), 1-7. doi:10.29292/jics.v17i2.631
NLM
Agopian PGD, Martino JA, Simoen E, Rooyackers R, Claeys C. Tunnel-FET evolution and applications for analog circuits [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-7.[citado 2024 out. 31 ] Available from: https://doi.org/10.29292/jics.v17i2.631
Vancouver
Agopian PGD, Martino JA, Simoen E, Rooyackers R, Claeys C. Tunnel-FET evolution and applications for analog circuits [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-7.[citado 2024 out. 31 ] Available from: https://doi.org/10.29292/jics.v17i2.631
Artigo de periodico
Experimental analysis of trade-off between transistor efficiency and unit gain frequency of nanosheet NMOSFET down to -100°C (2022)
Silva, Vanessa Cristina Pereira da; Leal, João Vitor da Costa; Perina, Welder F; Martino, João Antonio ; Simoen, Eddy ; Veloso, A; Agopian, Paula Ghedini Der
Fonte: Journal of Integrated Circuits and Systems. Unidade: EP
Assuntos: TRANSISTORES, NANOTECNOLOGIA, BAIXA TEMPERATURA
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ABNT
SILVA, Vanessa Cristina Pereira da et al. Experimental analysis of trade-off between transistor efficiency and unit gain frequency of nanosheet NMOSFET down to -100°C. Journal of Integrated Circuits and Systems, v. 17, n. 1, p. 1-6, 2022Tradução . . Disponível em: https://doi.org/10.29292/jics.v17il.550. Acesso em: 31 out. 2024.
APA
Silva, V. C. P. da, Leal, J. V. da C., Perina, W. F., Martino, J. A., Simoen, E., Veloso, A., & Agopian, P. G. D. (2022). Experimental analysis of trade-off between transistor efficiency and unit gain frequency of nanosheet NMOSFET down to -100°C. Journal of Integrated Circuits and Systems, 17( 1), 1-6. doi:10.29292/jics.v17i1.550
NLM
Silva VCP da, Leal JV da C, Perina WF, Martino JA, Simoen E, Veloso A, Agopian PGD. Experimental analysis of trade-off between transistor efficiency and unit gain frequency of nanosheet NMOSFET down to -100°C [Internet]. Journal of Integrated Circuits and Systems. 2022 ;17( 1): 1-6.[citado 2024 out. 31 ] Available from: https://doi.org/10.29292/jics.v17il.550
Vancouver
Silva VCP da, Leal JV da C, Perina WF, Martino JA, Simoen E, Veloso A, Agopian PGD. Experimental analysis of trade-off between transistor efficiency and unit gain frequency of nanosheet NMOSFET down to -100°C [Internet]. Journal of Integrated Circuits and Systems. 2022 ;17( 1): 1-6.[citado 2024 out. 31 ] Available from: https://doi.org/10.29292/jics.v17il.550
Artigo de periodico
Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature (2022)
Silva, Vanessa Cristina Pereira da; Martino, João Antonio ; Simoen, Eddy ; Veloso, Anabela; Agopian, Paula Ghedini Der
Fonte: Solid State Electronics. Unidade: EP
Assuntos: TRANSISTORES, ALTA TEMPERATURA
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ABNT
SILVA, Vanessa Cristina Pereira da et al. Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature. Solid State Electronics, v. 191, p. 1-8, 2022Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2022.108267. Acesso em: 31 out. 2024.
APA
Silva, V. C. P. da, Martino, J. A., Simoen, E., Veloso, A., & Agopian, P. G. D. (2022). Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature. Solid State Electronics, 191, 1-8. doi:10.1016/j.sse.2022.108267
NLM
Silva VCP da, Martino JA, Simoen E, Veloso A, Agopian PGD. Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature [Internet]. Solid State Electronics. 2022 ;191 1-8.[citado 2024 out. 31 ] Available from: https://doi.org/10.1016/j.sse.2022.108267
Vancouver
Silva VCP da, Martino JA, Simoen E, Veloso A, Agopian PGD. Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature [Internet]. Solid State Electronics. 2022 ;191 1-8.[citado 2024 out. 31 ] Available from: https://doi.org/10.1016/j.sse.2022.108267
Artigo de periodico
Analog performance of SOI nFinFETs with different TiN gate electrode thickness (2010)
Galeti, Milene; Rodrigues, Michele; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Fonte: Microelectronics Technology and Devices - SBMicro 2010. Unidade: EP
Assunto: TRANSISTORES
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ABNT
GALETI, Milene et al. Analog performance of SOI nFinFETs with different TiN gate electrode thickness. Microelectronics Technology and Devices - SBMicro 2010, v. 31, n. 1, p. 59-65, 2010Tradução . . Disponível em: https://doi.org/10.1149/1.3474142. Acesso em: 31 out. 2024.
APA
Galeti, M., Rodrigues, M., Collaert, N., Simoen, E., Claeys, C., & Martino, J. A. (2010). Analog performance of SOI nFinFETs with different TiN gate electrode thickness. Microelectronics Technology and Devices - SBMicro 2010, 31( 1), 59-65. doi:10.1149/1.3474142
NLM
Galeti M, Rodrigues M, Collaert N, Simoen E, Claeys C, Martino JA. Analog performance of SOI nFinFETs with different TiN gate electrode thickness [Internet]. Microelectronics Technology and Devices - SBMicro 2010. 2010 ;31( 1): 59-65.[citado 2024 out. 31 ] Available from: https://doi.org/10.1149/1.3474142
Vancouver
Galeti M, Rodrigues M, Collaert N, Simoen E, Claeys C, Martino JA. Analog performance of SOI nFinFETs with different TiN gate electrode thickness [Internet]. Microelectronics Technology and Devices - SBMicro 2010. 2010 ;31( 1): 59-65.[citado 2024 out. 31 ] Available from: https://doi.org/10.1149/1.3474142

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