Analysis of the self-heating effect in UTBOX devices (2012)
- Authors:
- Autor USP: MARTINO, JOÃO ANTONIO - EP
- Unidade: EP
- DOI: 10.1149/04901.0153ecst
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Publisher place: Pennington
- Date published: 2012
- Source:
- Conference titles: International Symposium on Microelectronics Technology and Devices
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
RODRIGUES, Michele et al. Analysis of the self-heating effect in UTBOX devices. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0153ecst. Acesso em: 26 jan. 2026. -
APA
Rodrigues, M., Cruz, E. O., Galeti, M., & Martino, J. A. (2012). Analysis of the self-heating effect in UTBOX devices. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0153ecst -
NLM
Rodrigues M, Cruz EO, Galeti M, Martino JA. Analysis of the self-heating effect in UTBOX devices [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2026 jan. 26 ] Available from: https://doi.org/10.1149/04901.0153ecst -
Vancouver
Rodrigues M, Cruz EO, Galeti M, Martino JA. Analysis of the self-heating effect in UTBOX devices [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2026 jan. 26 ] Available from: https://doi.org/10.1149/04901.0153ecst - Analog circuit design using graded-channel SOI NMOSFETs
- Extraction of the interface charge density at the silicon substrate interface in SOI MOSFET's at cryogenic temperatures
- Extraction of the interface and oxide charge density in silicon-on-insulator MOSFETs
- Projeto de um processo CMOS com cavidade dupla e dimensões de porta de 2 um
- Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time
- Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation
- Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results
- Estudo comparativo de estruturas de fonte e dreno de transistores mos submicrometricos
- Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices
- Effective channel length and series resistence extraction error induced by the substrate in enhancement-mode SOI nMOSFETs
Informações sobre o DOI: 10.1149/04901.0153ecst (Fonte: oaDOI API)
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