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Artigo de periodico
The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs (2017)
Bordallo, Caio Cesar Mendes ; Collaert, Nadine ; Claeys, Cor ; Simoen, Eddy ; Vandooren, A; Rooyackers, Rita; Mols, Yannick; Alian, A; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: IEEE Transactions on Electron Devices. Unidade: EP
Subjects: MICROELETRÔNICA, SEMICONDUTORES
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ABNT
BORDALLO, Caio Cesar Mendes et al. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs. IEEE Transactions on Electron Devices, v. 64, n. 9, p. 3595-3600, 2017Tradução . . Disponível em: https://doi.org/10.1109/ted.2017.2721110. Acesso em: 25 set. 2024.
APA
Bordallo, C. C. M., Collaert, N., Claeys, C., Simoen, E., Vandooren, A., Rooyackers, R., et al. (2017). The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs. IEEE Transactions on Electron Devices, 64( 9), 3595-3600. doi:10.1109/ted.2017.2721110
NLM
Bordallo CCM, Collaert N, Claeys C, Simoen E, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs [Internet]. IEEE Transactions on Electron Devices. 2017 ; 64( 9): 3595-3600.[citado 2024 set. 25 ] Available from: https://doi.org/10.1109/ted.2017.2721110
Vancouver
Bordallo CCM, Collaert N, Claeys C, Simoen E, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs [Internet]. IEEE Transactions on Electron Devices. 2017 ; 64( 9): 3595-3600.[citado 2024 set. 25 ] Available from: https://doi.org/10.1109/ted.2017.2721110
Artigo de periodico
Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes (2016)
Oliveira, Alberto Vinicius de; Agopian, Paula Ghedini Der ; Simoen, Eddy ; Langer, Robert; Collaert, Nadine ; Thean, Aaron; Claeys, Cor ; Martino, João Antonio
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: SEMICONDUTORES, MICROELETRÔNICA
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ABNT
OLIVEIRA, Alberto Vinicius de et al. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes. Semiconductor Science and Technology, v. 31, n. 11, p. 114002 , 2016Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/31/11/114002. Acesso em: 25 set. 2024.
APA
Oliveira, A. V. de, Agopian, P. G. D., Simoen, E., Langer, R., Collaert, N., Thean, A., et al. (2016). Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes. Semiconductor Science and Technology, 31( 11), 114002 . doi:10.1088/0268-1242/31/11/114002
NLM
Oliveira AV de, Agopian PGD, Simoen E, Langer R, Collaert N, Thean A, Claeys C, Martino JA. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114002 .[citado 2024 set. 25 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114002
Vancouver
Oliveira AV de, Agopian PGD, Simoen E, Langer R, Collaert N, Thean A, Claeys C, Martino JA. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114002 .[citado 2024 set. 25 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114002
Artigo de periodico
Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs (2016)
Oliveira, Alberto Vinicius de; Simoen, Eddy ; Thean, Aaron; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Claeys, Cor ; Mertens, Hans; Collaert, Nadine
Source: ECS Transactions volume 66 issue 5 on pages 309 to 314. Unidade: EP
Subjects: MICROELETRÔNICA, TRANSISTORES
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ABNT
OLIVEIRA, Alberto Vinicius de et al. Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs. ECS Transactions volume 66 issue 5 on pages 309 to 314, v. 66, n. 5, p. 309-314, 2016Tradução . . Disponível em: https://doi.org/10.1149/06605.0309ecst. Acesso em: 25 set. 2024.
APA
Oliveira, A. V. de, Simoen, E., Thean, A., Agopian, P. G. D., Martino, J. A., Claeys, C., et al. (2016). Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs. ECS Transactions volume 66 issue 5 on pages 309 to 314, 66( 5), 309-314. doi:10.1149/06605.0309ecst
NLM
Oliveira AV de, Simoen E, Thean A, Agopian PGD, Martino JA, Claeys C, Mertens H, Collaert N. Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs [Internet]. ECS Transactions volume 66 issue 5 on pages 309 to 314. 2016 ; 66( 5): 309-314.[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/06605.0309ecst
Vancouver
Oliveira AV de, Simoen E, Thean A, Agopian PGD, Martino JA, Claeys C, Mertens H, Collaert N. Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs [Internet]. ECS Transactions volume 66 issue 5 on pages 309 to 314. 2016 ; 66( 5): 309-314.[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/06605.0309ecst
Artigo de periodico
Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures (2016)
Oliveira, Alberto Vinicius de; Collaert, Nadine ; Thean, Aaron; Claeys, Cor ; Simoen, Eddy ; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Subjects: SEMICONDUTORES, MICROELETRÔNICA
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ABNT
OLIVEIRA, Alberto Vinicius de et al. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures. Solid-State Electronics, v. 123, p. 124-129, 2016Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2016.05.004. Acesso em: 25 set. 2024.
APA
Oliveira, A. V. de, Collaert, N., Thean, A., Claeys, C., Simoen, E., Agopian, P. G. D., & Martino, J. A. (2016). Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures. Solid-State Electronics, 123, 124-129. doi:10.1016/j.sse.2016.05.004
NLM
Oliveira AV de, Collaert N, Thean A, Claeys C, Simoen E, Agopian PGD, Martino JA. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures [Internet]. Solid-State Electronics. 2016 ; 123 124-129.[citado 2024 set. 25 ] Available from: https://doi.org/10.1016/j.sse.2016.05.004
Vancouver
Oliveira AV de, Collaert N, Thean A, Claeys C, Simoen E, Agopian PGD, Martino JA. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures [Internet]. Solid-State Electronics. 2016 ; 123 124-129.[citado 2024 set. 25 ] Available from: https://doi.org/10.1016/j.sse.2016.05.004
Artigo de periodico
Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs (2015)
Bühler, Rudolf Theoderich; Agopian, Paula Ghedini Der ; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
BÜHLER, Rudolf Theoderich et al. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs. Solid-State Electronics, v. 103, p. 209-215, 2015Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2014.07.010. Acesso em: 25 set. 2024.
APA
Bühler, R. T., Agopian, P. G. D., Collaert, N., Simoen, E., Claeys, C., & Martino, J. A. (2015). Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs. Solid-State Electronics, 103, 209-215. doi:10.1016/j.sse.2014.07.010
NLM
Bühler RT, Agopian PGD, Collaert N, Simoen E, Claeys C, Martino JA. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs [Internet]. Solid-State Electronics. 2015 ;103 209-215.[citado 2024 set. 25 ] Available from: https://doi.org/10.1016/j.sse.2014.07.010
Vancouver
Bühler RT, Agopian PGD, Collaert N, Simoen E, Claeys C, Martino JA. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs [Internet]. Solid-State Electronics. 2015 ;103 209-215.[citado 2024 set. 25 ] Available from: https://doi.org/10.1016/j.sse.2014.07.010
Artigo de periodico
Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation (2014)
Caño de Andrade, Maria Glória; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Aoulaiche, Marc; Martino, João Antonio
Source: Microelectronics Reliability. Unidade: EP
Subjects: SILÍCIO, MICROELETRÔNICA
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ABNT
CAÑO DE ANDRADE, Maria Glória et al. Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation. Microelectronics Reliability, v. 54, n. 11, p. 2349-2354, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.microrel.2014.06.013. Acesso em: 25 set. 2024.
APA
Caño de Andrade, M. G., Collaert, N., Simoen, E., Claeys, C., Aoulaiche, M., & Martino, J. A. (2014). Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation. Microelectronics Reliability, 54( 11), 2349-2354. doi:10.1016/j.microrel.2014.06.013
NLM
Caño de Andrade MG, Collaert N, Simoen E, Claeys C, Aoulaiche M, Martino JA. Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation [Internet]. Microelectronics Reliability. 2014 ; 54( 11): 2349-2354.[citado 2024 set. 25 ] Available from: https://doi.org/10.1016/j.microrel.2014.06.013
Vancouver
Caño de Andrade MG, Collaert N, Simoen E, Claeys C, Aoulaiche M, Martino JA. Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation [Internet]. Microelectronics Reliability. 2014 ; 54( 11): 2349-2354.[citado 2024 set. 25 ] Available from: https://doi.org/10.1016/j.microrel.2014.06.013
Trabalho de evento
UTBOX SOI devices with high-k gate dielectric under analog performance (2012)
Galeti, Milene; Rodrigues, Michele; Aoulaiche, Marc; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
GALETI, Milene et al. UTBOX SOI devices with high-k gate dielectric under analog performance. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0119ecst. Acesso em: 25 set. 2024.
APA
Galeti, M., Rodrigues, M., Aoulaiche, M., Collaert, N., Simoen, E., Claeys, C., & Martino, J. A. (2012). UTBOX SOI devices with high-k gate dielectric under analog performance. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0119ecst
NLM
Galeti M, Rodrigues M, Aoulaiche M, Collaert N, Simoen E, Claeys C, Martino JA. UTBOX SOI devices with high-k gate dielectric under analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0119ecst
Vancouver
Galeti M, Rodrigues M, Aoulaiche M, Collaert N, Simoen E, Claeys C, Martino JA. UTBOX SOI devices with high-k gate dielectric under analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 set. 25 ] Available from: https://doi.org/10.1149/04901.0119ecst
Trabalho de evento
Impact of TiN metal gate thickness and the HsSiO nitridation on MuGFETs electrical performance (2009)
Rodrigues, M; Mercha, A.; Simoen, Eddy ; Collaert, Nadine ; Claeys, Cor ; Martino, João Antonio
Source: Proceedings: ULIS 2009. Conference titles: International Conference on Ultimate Integration on Silicon. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
RODRIGUES, M et al. Impact of TiN metal gate thickness and the HsSiO nitridation on MuGFETs electrical performance. 2009, Anais.. New York: IEEE, 2009. . Acesso em: 25 set. 2024.
APA
Rodrigues, M., Mercha, A., Simoen, E., Collaert, N., Claeys, C., & Martino, J. A. (2009). Impact of TiN metal gate thickness and the HsSiO nitridation on MuGFETs electrical performance. In Proceedings: ULIS 2009. New York: IEEE.
NLM
Rodrigues M, Mercha A, Simoen E, Collaert N, Claeys C, Martino JA. Impact of TiN metal gate thickness and the HsSiO nitridation on MuGFETs electrical performance. Proceedings: ULIS 2009. 2009 ;[citado 2024 set. 25 ]
Vancouver
Rodrigues M, Mercha A, Simoen E, Collaert N, Claeys C, Martino JA. Impact of TiN metal gate thickness and the HsSiO nitridation on MuGFETs electrical performance. Proceedings: ULIS 2009. 2009 ;[citado 2024 set. 25 ]
Trabalho de evento
Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs (2008)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Simoen, Eddy ; Rooyackers, Rita; Collaert, Nadine ; Claeys, Cor
Source: SBMICRO 2008: Anais. Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
PAVANELLO, Marcelo Antonio et al. Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs. 2008, Anais.. Pennington: The Electrochemical Society, 2008. . Acesso em: 25 set. 2024.
APA
Pavanello, M. A., Martino, J. A., Simoen, E., Rooyackers, R., Collaert, N., & Claeys, C. (2008). Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs. In SBMICRO 2008: Anais. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Martino JA, Simoen E, Rooyackers R, Collaert N, Claeys C. Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs. SBMICRO 2008: Anais. 2008 ;[citado 2024 set. 25 ]
Vancouver
Pavanello MA, Martino JA, Simoen E, Rooyackers R, Collaert N, Claeys C. Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs. SBMICRO 2008: Anais. 2008 ;[citado 2024 set. 25 ]
Trabalho de evento
Low temperature operation of undoped body triple-gate finFETs from an analog perspective (2007)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Simoen, Eddy ; Rooyackers, Rita; Collaert, Nadine ; Claeys, Cor
Source: SBMicro 2007. Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
PAVANELLO, Marcelo Antonio et al. Low temperature operation of undoped body triple-gate finFETs from an analog perspective. 2007, Anais.. Pennington: The Electrochemical Society, 2007. . Acesso em: 25 set. 2024.
APA
Pavanello, M. A., Martino, J. A., Simoen, E., Rooyackers, R., Collaert, N., & Claeys, C. (2007). Low temperature operation of undoped body triple-gate finFETs from an analog perspective. In SBMicro 2007. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Martino JA, Simoen E, Rooyackers R, Collaert N, Claeys C. Low temperature operation of undoped body triple-gate finFETs from an analog perspective. SBMicro 2007. 2007 ;[citado 2024 set. 25 ]
Vancouver
Pavanello MA, Martino JA, Simoen E, Rooyackers R, Collaert N, Claeys C. Low temperature operation of undoped body triple-gate finFETs from an analog perspective. SBMicro 2007. 2007 ;[citado 2024 set. 25 ]

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