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Filtros : "Indexado no INSPEC" "Pavanello, Marcelo Antonio" Limpar

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1 - 9 (9 records)

  • Artigo de periodico

    Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor (2005)

    Cerdeira, Antonio ; Alemán, Miguel A.; Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis ; Vancaillie, Laurent

    Source: IEEE Transactions on Electron Devices. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS MOS

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    • ABNT

      CERDEIRA, Antonio et al. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor. IEEE Transactions on Electron Devices, v. 52, n. 5, p. 967-972, 2005Tradução . . Disponível em: https://doi.org/10.1109/ted.2005.846327. Acesso em: 28 ago. 2024.

    • APA

      Cerdeira, A., Alemán, M. A., Pavanello, M. A., Martino, J. A., Flandre, D., & Vancaillie, L. (2005). Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor. IEEE Transactions on Electron Devices, 52( 5), 967-972. doi:10.1109/ted.2005.846327

    • NLM

      Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Flandre D, Vancaillie L. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor [Internet]. IEEE Transactions on Electron Devices. 2005 ;52( 5): 967-972.[citado 2024 ago. 28 ] Available from: https://doi.org/10.1109/ted.2005.846327

    • Vancouver

      Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Flandre D, Vancaillie L. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor [Internet]. IEEE Transactions on Electron Devices. 2005 ;52( 5): 967-972.[citado 2024 ago. 28 ] Available from: https://doi.org/10.1109/ted.2005.846327

  • Artigo de periodico

    Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body (2002)

    Pavanello, Marcelo Antonio ; Martino, João Antonio ; Mercha, A.; Rafi, J.M.; Simoen, Eddy ; Claeys, Cor ; Van Meer, H.; De Meyer, K.

    Source: Journal de Physique IV. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS MOS

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    • ABNT

      PAVANELLO, Marcelo Antonio et al. Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV, v. 12, n. 3, 2002Tradução . . Acesso em: 28 ago. 2024.

    • APA

      Pavanello, M. A., Martino, J. A., Mercha, A., Rafi, J. M., Simoen, E., Claeys, C., et al. (2002). Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV, 12( 3).

    • NLM

      Pavanello MA, Martino JA, Mercha A, Rafi JM, Simoen E, Claeys C, Van Meer H, De Meyer K. Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV. 2002 ;12( 3):[citado 2024 ago. 28 ]

    • Vancouver

      Pavanello MA, Martino JA, Mercha A, Rafi JM, Simoen E, Claeys C, Van Meer H, De Meyer K. Low temperature operation of 0.13 'mü' partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV. 2002 ;12( 3):[citado 2024 ago. 28 ]

  • Artigo de periodico

    Low temperature operation of graded-channel SOI nMOSFETs for analog applications (2002)

    Pavanello, Marcelo Antonio ; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Flandre, Denis

    Source: Journal de Physique IV. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS MOS

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      PAVANELLO, Marcelo Antonio et al. Low temperature operation of graded-channel SOI nMOSFETs for analog applications. Journal de Physique IV, v. 12, n. 3, 2002Tradução . . Disponível em: https://doi.org/10.1051/jp420020030. Acesso em: 28 ago. 2024.

    • APA

      Pavanello, M. A., Agopian, P. G. D., Martino, J. A., & Flandre, D. (2002). Low temperature operation of graded-channel SOI nMOSFETs for analog applications. Journal de Physique IV, 12( 3). doi:10.1051/jp420020030

    • NLM

      Pavanello MA, Agopian PGD, Martino JA, Flandre D. Low temperature operation of graded-channel SOI nMOSFETs for analog applications [Internet]. Journal de Physique IV. 2002 ;12( 3):[citado 2024 ago. 28 ] Available from: https://doi.org/10.1051/jp420020030

    • Vancouver

      Pavanello MA, Agopian PGD, Martino JA, Flandre D. Low temperature operation of graded-channel SOI nMOSFETs for analog applications [Internet]. Journal de Physique IV. 2002 ;12( 3):[citado 2024 ago. 28 ] Available from: https://doi.org/10.1051/jp420020030

  • Artigo de periodico

    Analog circuit design using graded-channel silicon-on-insulator nMOSFETs (2002)

    Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis

    Source: Solid-State Electronics. Unidade: EP

    Assunto: CIRCUITOS ANALÓGICOS

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    • ABNT

      PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs. Solid-State Electronics, v. 46, n. 8, p. 1215-1225, 2002Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(02)00020-5. Acesso em: 28 ago. 2024.

    • APA

      Pavanello, M. A., Martino, J. A., & Flandre, D. (2002). Analog circuit design using graded-channel silicon-on-insulator nMOSFETs. Solid-State Electronics, 46( 8), 1215-1225. doi:10.1016/s0038-1101(02)00020-5

    • NLM

      Pavanello MA, Martino JA, Flandre D. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs [Internet]. Solid-State Electronics. 2002 ; 46( 8): 1215-1225.[citado 2024 ago. 28 ] Available from: https://doi.org/10.1016/s0038-1101(02)00020-5

    • Vancouver

      Pavanello MA, Martino JA, Flandre D. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs [Internet]. Solid-State Electronics. 2002 ; 46( 8): 1215-1225.[citado 2024 ago. 28 ] Available from: https://doi.org/10.1016/s0038-1101(02)00020-5

  • Artigo de periodico

    Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects (2000)

    Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis

    Source: Solid-State Electronics. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS

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    • ABNT

      PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, v. 44, n. 6, p. 917-922, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00032-0. Acesso em: 28 ago. 2024.

    • APA

      Pavanello, M. A., Martino, J. A., & Flandre, D. (2000). Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, 44( 6), 917-922. doi:10.1016/s0038-1101(00)00032-0

    • NLM

      Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2024 ago. 28 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0

    • Vancouver

      Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2024 ago. 28 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0

  • Artigo de periodico

    An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics (2000)

    Pavanello, Marcelo Antonio ; Martino, João Antonio ; Dessard, Vincent; Flandre, Denis

    Source: Electrochemical and Solid-State Letters. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS MOS

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    • ABNT

      PAVANELLO, Marcelo Antonio et al. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics. Electrochemical and Solid-State Letters, v. 3, n. Ja 2000, p. 50-52, 2000Tradução . . Disponível em: https://doi.org/10.1149/1.1390955. Acesso em: 28 ago. 2024.

    • APA

      Pavanello, M. A., Martino, J. A., Dessard, V., & Flandre, D. (2000). An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics. Electrochemical and Solid-State Letters, 3( Ja 2000), 50-52. doi:10.1149/1.1390955

    • NLM

      Pavanello MA, Martino JA, Dessard V, Flandre D. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics [Internet]. Electrochemical and Solid-State Letters. 2000 ; 3( Ja 2000): 50-52.[citado 2024 ago. 28 ] Available from: https://doi.org/10.1149/1.1390955

    • Vancouver

      Pavanello MA, Martino JA, Dessard V, Flandre D. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics [Internet]. Electrochemical and Solid-State Letters. 2000 ; 3( Ja 2000): 50-52.[citado 2024 ago. 28 ] Available from: https://doi.org/10.1149/1.1390955

  • Artigo de periodico

    Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's (1999)

    Pavanello, Marcelo Antonio ; Martino, João Antonio

    Source: Solid-State Electronics. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS MOS

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    • ABNT

      PAVANELLO, Marcelo Antonio e MARTINO, João Antonio. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's. Solid-State Electronics, 1999Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(99)00178-1. Acesso em: 28 ago. 2024.

    • APA

      Pavanello, M. A., & Martino, J. A. (1999). Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's. Solid-State Electronics. doi:10.1016/s0038-1101(99)00178-1

    • NLM

      Pavanello MA, Martino JA. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's [Internet]. Solid-State Electronics. 1999 ;[citado 2024 ago. 28 ] Available from: https://doi.org/10.1016/s0038-1101(99)00178-1

    • Vancouver

      Pavanello MA, Martino JA. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's [Internet]. Solid-State Electronics. 1999 ;[citado 2024 ago. 28 ] Available from: https://doi.org/10.1016/s0038-1101(99)00178-1

  • Artigo de periodico

    Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k (1997)

    Pavanello, Marcelo Antonio ; Martino, João Antonio ; Colinge, Jean-Pierre

    Source: Microelectronic Engineering. Unidade: EP

    Assunto: MICROELETRÔNICA

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      PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k. Microelectronic Engineering, v. 36, n. 1-4, p. 375-378, 1997Tradução . . Disponível em: https://doi.org/10.1016/s0167-9317(97)00083-x. Acesso em: 28 ago. 2024.

    • APA

      Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1997). Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k. Microelectronic Engineering, 36( 1-4), 375-378. doi:10.1016/s0167-9317(97)00083-x

    • NLM

      Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k [Internet]. Microelectronic Engineering. 1997 ; 36( 1-4): 375-378.[citado 2024 ago. 28 ] Available from: https://doi.org/10.1016/s0167-9317(97)00083-x

    • Vancouver

      Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k [Internet]. Microelectronic Engineering. 1997 ; 36( 1-4): 375-378.[citado 2024 ago. 28 ] Available from: https://doi.org/10.1016/s0167-9317(97)00083-x

  • Artigo de periodico

    Theoretical and experimental study of the substrate effect on the fully depleted SOI MOSFET at low temperatures (1996)

    Pavanello, Marcelo Antonio ; Martino, João Antonio ; Colinge, Jean-Pierre

    Source: Journal de Physique IV Colloque 3, supplement au Journal de Physique III. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS MOS

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      PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Theoretical and experimental study of the substrate effect on the fully depleted SOI MOSFET at low temperatures. Journal de Physique IV Colloque 3, supplement au Journal de Physique III, v. 6, 1996Tradução . . Acesso em: 28 ago. 2024.

    • APA

      Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1996). Theoretical and experimental study of the substrate effect on the fully depleted SOI MOSFET at low temperatures. Journal de Physique IV Colloque 3, supplement au Journal de Physique III, 6.

    • NLM

      Pavanello MA, Martino JA, Colinge J-P. Theoretical and experimental study of the substrate effect on the fully depleted SOI MOSFET at low temperatures. Journal de Physique IV Colloque 3, supplement au Journal de Physique III. 1996 ;6[citado 2024 ago. 28 ]

    • Vancouver

      Pavanello MA, Martino JA, Colinge J-P. Theoretical and experimental study of the substrate effect on the fully depleted SOI MOSFET at low temperatures. Journal de Physique IV Colloque 3, supplement au Journal de Physique III. 1996 ;6[citado 2024 ago. 28 ]
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