Lina: timing-constrained high-level synthesis performance estimator for fast DSE (2019)
Source: Proceedings. Conference titles: International Conference on Field-Programmable Technology - ICFPT. Unidade: ICMC
Subjects: CIRCUITOS FPGA, BENCHMARKS
ABNT
PERINA, André Bannwart e BECKER, Jürgen e BONATO, Vanderlei. Lina: timing-constrained high-level synthesis performance estimator for fast DSE. 2019, Anais.. Los Alamitos: IEEE, 2019. Disponível em: https://doi.org/10.1109/ICFPT47387.2019.00063. Acesso em: 09 jul. 2024.APA
Perina, A. B., Becker, J., & Bonato, V. (2019). Lina: timing-constrained high-level synthesis performance estimator for fast DSE. In Proceedings. Los Alamitos: IEEE. doi:10.1109/ICFPT47387.2019.00063NLM
Perina AB, Becker J, Bonato V. Lina: timing-constrained high-level synthesis performance estimator for fast DSE [Internet]. Proceedings. 2019 ;[citado 2024 jul. 09 ] Available from: https://doi.org/10.1109/ICFPT47387.2019.00063Vancouver
Perina AB, Becker J, Bonato V. Lina: timing-constrained high-level synthesis performance estimator for fast DSE [Internet]. Proceedings. 2019 ;[citado 2024 jul. 09 ] Available from: https://doi.org/10.1109/ICFPT47387.2019.00063