A 4.1 GHz dual modulus prescaler using the E-TSPC technique and double data throughput structures (2007)
- Authors:
- USP affiliated authors: SOARES JUNIOR, JOAO NAVARRO - EESC ; NOIJE, WILHELMUS ADRIANUS MARIA VAN - EP
- Schools: EESC; EP
- Subjects: CIRCUITOS ELETRÔNICOS; CIRCUITOS INTEGRADOS MOS
- Language: Inglês
- Imprenta:
- Publisher: IEEE
- Place of publication: New Orleans
- Date published: 2007
- ISBN: 1424409217
- Conference title: IEEE International Symposium on Circuits and Systems
-
ABNT
MIRANDA, Fernando Pedro Henriques de; SOARES JUNIOR, João Navarro; VAN NOIJE, Wilhelmus Adrianus Maria. A 4.1 GHz dual modulus prescaler using the E-TSPC technique and double data throughput structures. Anais.. New Orleans: IEEE, 2007. -
APA
Miranda, F. P. H. de, Soares Junior, J. N., & Van Noije, W. A. M. (2007). A 4.1 GHz dual modulus prescaler using the E-TSPC technique and double data throughput structures. In . New Orleans: IEEE. -
NLM
Miranda FPH de, Soares Junior JN, Van Noije WAM. A 4.1 GHz dual modulus prescaler using the E-TSPC technique and double data throughput structures. 2007 ; -
Vancouver
Miranda FPH de, Soares Junior JN, Van Noije WAM. A 4.1 GHz dual modulus prescaler using the E-TSPC technique and double data throughput structures. 2007 ; - A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer
- Implementation of analog circuits on digital sea of gates
- E-TSPC: extended true single-phase-clock MOS circuit technique for high speed applications
- The use of extended TSPC CMOS structures to build circuits with doubled input/output data throughput
- Conversores D/A de 6 bits desenvolvido em pre-difundido do tipo mar de transistores
- Metastability behavior of mismatched cmos flip-flops using state diagram analysis
- Recuperador de clock em estrutura gate array do tipo mar de transistores
- Precise final state determination of mismatched cmos latches
- A 1.6 GHz dual modulus prescaler using the extended true single-phase-clock CMOS circuit technique (E-TSPC)
- Fully integrated cmos clock recovery at gbits / rates
How to cite
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
