Fully integrated cmos clock recovery at gbits / rates (1996)
- Authors:
- USP affiliated authors: SOARES JUNIOR, JOAO NAVARRO - EP ; NOIJE, WILHELMUS ADRIANUS MARIA VAN - EP
- Unidade: EP
- Assunto: CIRCUITOS INTEGRADOS
- Language: Inglês
- Imprenta:
- Source:
- Título: Proceedings
- Conference titles: Conference of the Brazilian Microelectronics Society
-
ABNT
MOREIRA, L C et al. Fully integrated cmos clock recovery at gbits / rates. 1996, Anais.. São Paulo: Sbmicro, 1996. . Acesso em: 05 out. 2024. -
APA
Moreira, L. C., Toma, M., Soares Junior, J. N., & Van Noije, W. A. M. (1996). Fully integrated cmos clock recovery at gbits / rates. In Proceedings. São Paulo: Sbmicro. -
NLM
Moreira LC, Toma M, Soares Junior JN, Van Noije WAM. Fully integrated cmos clock recovery at gbits / rates. Proceedings. 1996 ;[citado 2024 out. 05 ] -
Vancouver
Moreira LC, Toma M, Soares Junior JN, Van Noije WAM. Fully integrated cmos clock recovery at gbits / rates. Proceedings. 1996 ;[citado 2024 out. 05 ] - A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer
- Implementation of analog circuits on digital sea of gates
- E-TSPC: extended true single-phase-clock MOS circuit technique for high speed applications
- A 4.1 GHz dual modulus prescaler using the E-TSPC technique and double data throughput structures
- Metodos de teste de conversores a / d e sua aplicacao em projeto
- Analog circuits on sog gate arrays: an 100mhz 6-bit d / a converter
- Precise final state determination of cmos latches
- Analysis of the histogram testing applied to obtain the effective bit number of adc
- High speed cmos ecl-compatible input circuit
- Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design
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