Precise final state determination of mismatched cmos latches (1995)
- Authors:
- USP affiliated authors: SOARES JUNIOR, JOAO NAVARRO - EP ; NOIJE, WILHELMUS ADRIANUS MARIA VAN - EP
- Unidade: EP
- Assunto: CIRCUITOS INTEGRADOS
- Language: Inglês
- Imprenta:
- Source:
- Título: Ieee Journal of Solid-State Circuits
- Volume/Número/Paginação/Ano: v.30, n.5 , p.607-11, mai. 1995
-
ABNT
VAN NOIJE, Wilhelmus Adrianus Maria e LIU, W T e SOARES JUNIOR, João Navarro. Precise final state determination of mismatched cmos latches. Ieee Journal of Solid-State Circuits, v. 30, n. 5 , p. 607-11, 1995Tradução . . Acesso em: 23 jan. 2026. -
APA
Van Noije, W. A. M., Liu, W. T., & Soares Junior, J. N. (1995). Precise final state determination of mismatched cmos latches. Ieee Journal of Solid-State Circuits, 30( 5 ), 607-11. -
NLM
Van Noije WAM, Liu WT, Soares Junior JN. Precise final state determination of mismatched cmos latches. Ieee Journal of Solid-State Circuits. 1995 ;30( 5 ): 607-11.[citado 2026 jan. 23 ] -
Vancouver
Van Noije WAM, Liu WT, Soares Junior JN. Precise final state determination of mismatched cmos latches. Ieee Journal of Solid-State Circuits. 1995 ;30( 5 ): 607-11.[citado 2026 jan. 23 ] - Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design
- Conversores D/A de 6 bits desenvolvido em pre-difundido do tipo mar de transistores
- The use of extended TSPC CMOS structures to build circuits with doubled input/output data throughput
- Analysis of the histogram testing applied to obtain the effective bit number for ADC
- Implementation of analog circuits on digital sea of gates
- E-TSPC: extended true single-phase-clock MOS circuit technique for high speed applications
- A 1.6 GHz dual modulus prescaler using the extended true single-phase-clock CMOS circuit technique (E-TSPC)
- A small area 8 bits 50 MHz CMOS DAC for bluetooth transmitter
- Analog circuits on sog gate arrays: an 100mhz 6-bit d / a converter
- Precise final state determination of cmos latches
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