Impact of the graded-channel architecture on double gate transistors for high-performance analog applications (2003)
- Autores:
- Autores USP: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- Assunto: MICROELETRÔNICA
- Idioma: Inglês
- Imprenta:
- Editora: The Electrochemical Society
- Local: Pennington
- Data de publicação: 2003
- Fonte:
- Título do periódico: Silicon-on-Insulator Technology and Devices XI: proceedings
- Nome do evento: International Symposium on SOI Technology and Devices
-
ABNT
PAVANELLO, Marcelo Antonio et al. Impact of the graded-channel architecture on double gate transistors for high-performance analog applications. Silicon-on-Insulator Technology and Devices XI: proceedings. Tradução . Pennington: The Electrochemical Society, 2003. . . Acesso em: 18 set. 2024. -
APA
Pavanello, M. A., Martino, J. A., Chung, T. M., Kranti, A., Raskin, J. -P., & Flandre, D. (2003). Impact of the graded-channel architecture on double gate transistors for high-performance analog applications. In Silicon-on-Insulator Technology and Devices XI: proceedings. Pennington: The Electrochemical Society. -
NLM
Pavanello MA, Martino JA, Chung TM, Kranti A, Raskin J-P, Flandre D. Impact of the graded-channel architecture on double gate transistors for high-performance analog applications. In: Silicon-on-Insulator Technology and Devices XI: proceedings. Pennington: The Electrochemical Society; 2003. [citado 2024 set. 18 ] -
Vancouver
Pavanello MA, Martino JA, Chung TM, Kranti A, Raskin J-P, Flandre D. Impact of the graded-channel architecture on double gate transistors for high-performance analog applications. In: Silicon-on-Insulator Technology and Devices XI: proceedings. Pennington: The Electrochemical Society; 2003. [citado 2024 set. 18 ] - Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range
- Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures
- Comparison between conventional and graded-channel SOI nMOSFETs in low temperature operation
- Analog performance of graded-channel SOI NMOSFETS at low temperatures
- Comparison between 0.13Mm partially-depleted silicon-on-insulator technology with floating body operation at 300 K and 90 K
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
- Analysis of HALO implant influence on the self-heating and self-heating enhanced impact ionization on 0.13 Mm floating-body partially-depleted SOI MOSFET at low temperature
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