Analysis of HALO implant influence on the self-heating and self-heating enhanced impact ionization on 0.13μm floating-body partially-depleted SOI MOSFET at low temperature (2003)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Publisher place: Pennington
- Date published: 2003
- Source:
- Conference titles: International Symposium on SOI Technology and Devices
-
ABNT
PAVANELLO, Marcelo Antonio et al. Analysis of HALO implant influence on the self-heating and self-heating enhanced impact ionization on 0.13μm floating-body partially-depleted SOI MOSFET at low temperature. Silicon-on-Insulator Technology and Devices XI. Tradução . Pennington: The Electrochemical Society, 2003. . . Acesso em: 13 fev. 2026. -
APA
Pavanello, M. A., Martino, J. A., Simoen, E., Mercha, A., Claeys, C., Van Meer, H., & De Meyer, K. (2003). Analysis of HALO implant influence on the self-heating and self-heating enhanced impact ionization on 0.13μm floating-body partially-depleted SOI MOSFET at low temperature. In Silicon-on-Insulator Technology and Devices XI.. Pennington: The Electrochemical Society. -
NLM
Pavanello MA, Martino JA, Simoen E, Mercha A, Claeys C, Van Meer H, De Meyer K. Analysis of HALO implant influence on the self-heating and self-heating enhanced impact ionization on 0.13μm floating-body partially-depleted SOI MOSFET at low temperature. In: Silicon-on-Insulator Technology and Devices XI. Pennington: The Electrochemical Society; 2003. [citado 2026 fev. 13 ] -
Vancouver
Pavanello MA, Martino JA, Simoen E, Mercha A, Claeys C, Van Meer H, De Meyer K. Analysis of HALO implant influence on the self-heating and self-heating enhanced impact ionization on 0.13μm floating-body partially-depleted SOI MOSFET at low temperature. In: Silicon-on-Insulator Technology and Devices XI. Pennington: The Electrochemical Society; 2003. [citado 2026 fev. 13 ] - Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs
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- Operation of double gate graded-channel transistors at low temperatures
- Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature
- Analog performance of graded-channel SOI NMOSFETS at low temperatures
- A simple analytical model of graded-channel SOI nMOSFET transconductance
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
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