E-TSPC: extended true single-phase-clock MOS circuit technique for high speed applications (1997)
- Authors:
- USP affiliated authors: SOARES JUNIOR, JOAO NAVARRO - EP ; NOIJE, WILHELMUS ADRIANUS MARIA VAN - EP
- Unidade: EP
- Assunto: CIRCUITOS INTEGRADOS
- Language: Inglês
- Imprenta:
- Source:
- Título do periódico: Journal of Solid-State Devices and Circuits
- Volume/Número/Paginação/Ano: v. 5, n. 2, p. 21-26, jul. 1997
-
ABNT
SOARES JUNIOR, João Navarro e VAN NOIJE, Wilhelmus Adrianus Maria. E-TSPC: extended true single-phase-clock MOS circuit technique for high speed applications. Journal of Solid-State Devices and Circuits, v. 5, n. 2, p. 21-26, 1997Tradução . . Acesso em: 19 set. 2024. -
APA
Soares Junior, J. N., & Van Noije, W. A. M. (1997). E-TSPC: extended true single-phase-clock MOS circuit technique for high speed applications. Journal of Solid-State Devices and Circuits, 5( 2), 21-26. -
NLM
Soares Junior JN, Van Noije WAM. E-TSPC: extended true single-phase-clock MOS circuit technique for high speed applications. Journal of Solid-State Devices and Circuits. 1997 ; 5( 2): 21-26.[citado 2024 set. 19 ] -
Vancouver
Soares Junior JN, Van Noije WAM. E-TSPC: extended true single-phase-clock MOS circuit technique for high speed applications. Journal of Solid-State Devices and Circuits. 1997 ; 5( 2): 21-26.[citado 2024 set. 19 ] - A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer
- Implementation of analog circuits on digital sea of gates
- A 4.1 GHz dual modulus prescaler using the E-TSPC technique and double data throughput structures
- Recuperador de clock em estrutura gate array do tipo mar de transistores
- Precise final state determination of mismatched cmos latches
- Fully integrated cmos clock recovery at gbits / rates
- A 1.6 GHz dual modulus prescaler using the extended true single-phase-clock CMOS circuit technique (E-TSPC)
- Metodos de teste de conversores a / d e sua aplicacao em projeto
- Analog circuits on sog gate arrays: an 100mhz 6-bit d / a converter
- Precise final state determination of cmos latches
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