A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer (2005)
- Authors:
- USP affiliated authors: SOARES JUNIOR, JOAO NAVARRO - EP ; NOIJE, WILHELMUS ADRIANUS MARIA VAN - EP
- Unidade: EP
- Assunto: CIRCUITOS INTEGRADOS MOS
- Language: Inglês
- Imprenta:
- Source:
- Título: SBCCI 2005
- Conference titles: Symposium on Integrated Circuits and Systems Design
-
ABNT
GÓMEZ ARGÜELLO, Angel María e SOARES JUNIOR, João Navarro e VAN NOIJE, Wilhelmus Adrianus Maria. A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer. 2005, Anais.. New York: ACM, 2005. . Acesso em: 01 dez. 2025. -
APA
Gómez Argüello, A. M., Soares Junior, J. N., & Van Noije, W. A. M. (2005). A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer. In SBCCI 2005. New York: ACM. -
NLM
Gómez Argüello AM, Soares Junior JN, Van Noije WAM. A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer. SBCCI 2005. 2005 ;[citado 2025 dez. 01 ] -
Vancouver
Gómez Argüello AM, Soares Junior JN, Van Noije WAM. A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer. SBCCI 2005. 2005 ;[citado 2025 dez. 01 ] - Implementation of analog circuits on digital sea of gates
- E-TSPC: extended true single-phase-clock MOS circuit technique for high speed applications
- A 4.1 GHz dual modulus prescaler using the E-TSPC technique and double data throughput structures
- Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design
- Analog circuits on sog gate arrays: an 100mhz 6-bit d / a converter
- Precise final state determination of cmos latches
- High speed cmos ecl-compatible input circuit
- Metodos de teste de conversores a / d e sua aplicacao em projeto
- Analysis of the histogram testing applied to obtain the effective bit number for ADC
- Precise final state determination of mismatched cmos latches
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