ReP USP - Resultado da busca

Artigo de periodico
Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures (2001)
Bellodi, Marcello; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BELLODI, Marcello e MARTINO, João Antonio. Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures. Solid-State Electronics, v. 45, n. 5, p. 683-688, 2001Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(01)00099-5. Acesso em: 09 set. 2024.
APA
Bellodi, M., & Martino, J. A. (2001). Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures. Solid-State Electronics, 45( 5), 683-688. doi:10.1016/s0038-1101(01)00099-5
NLM
Bellodi M, Martino JA. Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures [Internet]. Solid-State Electronics. 2001 ; 45( 5): 683-688.[citado 2024 set. 09 ] Available from: https://doi.org/10.1016/s0038-1101(01)00099-5
Vancouver
Bellodi M, Martino JA. Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures [Internet]. Solid-State Electronics. 2001 ; 45( 5): 683-688.[citado 2024 set. 09 ] Available from: https://doi.org/10.1016/s0038-1101(01)00099-5
Artigo de periodico
Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs (2000)
Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
NICOLETT, Aparecido Sirley et al. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs. Solid-State Electronics, v. No 2000, n. 11, p. 1961-1969, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00166-0. Acesso em: 09 set. 2024.
APA
Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2000). Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs. Solid-State Electronics, No 2000( 11), 1961-1969. doi:10.1016/s0038-1101(00)00166-0
NLM
Nicolett AS, Martino JA, Simoen E, Claeys C. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs [Internet]. Solid-State Electronics. 2000 ; No 2000( 11): 1961-1969.[citado 2024 set. 09 ] Available from: https://doi.org/10.1016/s0038-1101(00)00166-0
Vancouver
Nicolett AS, Martino JA, Simoen E, Claeys C. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs [Internet]. Solid-State Electronics. 2000 ; No 2000( 11): 1961-1969.[citado 2024 set. 09 ] Available from: https://doi.org/10.1016/s0038-1101(00)00166-0
Artigo de periodico
Analog performance and application of graded-channel fully depleted SOI MOSFETs (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Dessard, Vincent; Flandre, Denis
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Analog performance and application of graded-channel fully depleted SOI MOSFETs. Solid-State Electronics, v. 44, n. 7, p. 1219-1222, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00034-4. Acesso em: 09 set. 2024.
APA
Pavanello, M. A., Martino, J. A., Dessard, V., & Flandre, D. (2000). Analog performance and application of graded-channel fully depleted SOI MOSFETs. Solid-State Electronics, 44( 7), 1219-1222. doi:10.1016/s0038-1101(00)00034-4
NLM
Pavanello MA, Martino JA, Dessard V, Flandre D. Analog performance and application of graded-channel fully depleted SOI MOSFETs [Internet]. Solid-State Electronics. 2000 ; 44( 7): 1219-1222.[citado 2024 set. 09 ] Available from: https://doi.org/10.1016/s0038-1101(00)00034-4
Vancouver
Pavanello MA, Martino JA, Dessard V, Flandre D. Analog performance and application of graded-channel fully depleted SOI MOSFETs [Internet]. Solid-State Electronics. 2000 ; 44( 7): 1219-1222.[citado 2024 set. 09 ] Available from: https://doi.org/10.1016/s0038-1101(00)00034-4
Artigo de periodico
Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, v. 44, n. 6, p. 917-922, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00032-0. Acesso em: 09 set. 2024.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2000). Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, 44( 6), 917-922. doi:10.1016/s0038-1101(00)00032-0
NLM
Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2024 set. 09 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0
Vancouver
Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2024 set. 09 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0
Artigo de periodico
Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect (2000)
Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
NICOLETT, Aparecido Sirley et al. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect. Solid-State Electronics, v. 44, n. 4, p. 677-684, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(99)00293-2. Acesso em: 09 set. 2024.
APA
Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2000). Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect. Solid-State Electronics, 44( 4), 677-684. doi:10.1016/s0038-1101(99)00293-2
NLM
Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect [Internet]. Solid-State Electronics. 2000 ; 44( 4): 677-684.[citado 2024 set. 09 ] Available from: https://doi.org/10.1016/s0038-1101(99)00293-2
Vancouver
Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect [Internet]. Solid-State Electronics. 2000 ; 44( 4): 677-684.[citado 2024 set. 09 ] Available from: https://doi.org/10.1016/s0038-1101(99)00293-2
Artigo de periodico
Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature (1997)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Colinge, Jean-Pierre
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature. Solid-State Electronics, v. 41, n. 9, p. 1241-1246, 1997Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(97)00071-3. Acesso em: 09 set. 2024.
APA
Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1997). Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature. Solid-State Electronics, 41( 9), 1241-1246. doi:10.1016/s0038-1101(97)00071-3
NLM
Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature [Internet]. Solid-State Electronics. 1997 ; 41( 9): 1241-1246.[citado 2024 set. 09 ] Available from: https://doi.org/10.1016/s0038-1101(97)00071-3
Vancouver
Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature [Internet]. Solid-State Electronics. 1997 ; 41( 9): 1241-1246.[citado 2024 set. 09 ] Available from: https://doi.org/10.1016/s0038-1101(97)00071-3
Artigo de periodico
Substrate influences on fully depleted enhacement mode SOI MOSFETs at room temperature and 77 K (1997)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Colinge, Jean-Pierre
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Substrate influences on fully depleted enhacement mode SOI MOSFETs at room temperature and 77 K. Solid-State Electronics, v. 41, n. ja 1997, p. 111-119, 1997Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(96)00126-8. Acesso em: 09 set. 2024.
APA
Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1997). Substrate influences on fully depleted enhacement mode SOI MOSFETs at room temperature and 77 K. Solid-State Electronics, 41( ja 1997), 111-119. doi:10.1016/s0038-1101(96)00126-8
NLM
Pavanello MA, Martino JA, Colinge J-P. Substrate influences on fully depleted enhacement mode SOI MOSFETs at room temperature and 77 K [Internet]. Solid-State Electronics. 1997 ; 41( ja 1997): 111-119.[citado 2024 set. 09 ] Available from: https://doi.org/10.1016/s0038-1101(96)00126-8
Vancouver
Pavanello MA, Martino JA, Colinge J-P. Substrate influences on fully depleted enhacement mode SOI MOSFETs at room temperature and 77 K [Internet]. Solid-State Electronics. 1997 ; 41( ja 1997): 111-119.[citado 2024 set. 09 ] Available from: https://doi.org/10.1016/s0038-1101(96)00126-8
Trabalho de evento
Fabrication process of free-standing polysilicon microfilaments using PECVD silicon oxide as a sacrifical layer (1997)
Simões, Eliphas Wagner; Furlan, Rogério ; Morimoto, Nilton Itiro ; Bonnaud, Olivier; Silva, Ana Neilde Rodrigues da
Source: Micromechanics Europe 97 : technical digest. Conference titles: Workshop on Micromachines, Micromechanics & Microsyems. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SIMÕES, Eliphas Wagner et al. Fabrication process of free-standing polysilicon microfilaments using PECVD silicon oxide as a sacrifical layer. 1997, Anais.. Southampton: University of Southampton, 1997. . Acesso em: 09 set. 2024.
APA
Simões, E. W., Furlan, R., Morimoto, N. I., Bonnaud, O., & Silva, A. N. R. da. (1997). Fabrication process of free-standing polysilicon microfilaments using PECVD silicon oxide as a sacrifical layer. In Micromechanics Europe 97 : technical digest. Southampton: University of Southampton.
NLM
Simões EW, Furlan R, Morimoto NI, Bonnaud O, Silva ANR da. Fabrication process of free-standing polysilicon microfilaments using PECVD silicon oxide as a sacrifical layer. Micromechanics Europe 97 : technical digest. 1997 ;[citado 2024 set. 09 ]
Vancouver
Simões EW, Furlan R, Morimoto NI, Bonnaud O, Silva ANR da. Fabrication process of free-standing polysilicon microfilaments using PECVD silicon oxide as a sacrifical layer. Micromechanics Europe 97 : technical digest. 1997 ;[citado 2024 set. 09 ]
Artigo de periodico
Mechanisms of surface roughness induced in silicon by fluorine containing plasmas (1997)
Mansano, Ronaldo Domingues ; Verdonck, Patrick Bernard; Maciel, Homero Santiago
Source: Vaccum. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MANSANO, Ronaldo Domingues e VERDONCK, Patrick Bernard e MACIEL, Homero Santiago. Mechanisms of surface roughness induced in silicon by fluorine containing plasmas. Vaccum, v. 48, n. 7-9, p. 677-679, 1997Tradução . . Disponível em: https://doi.org/10.1016/s0042-207x(97)00067-5. Acesso em: 09 set. 2024.
APA
Mansano, R. D., Verdonck, P. B., & Maciel, H. S. (1997). Mechanisms of surface roughness induced in silicon by fluorine containing plasmas. Vaccum, 48( 7-9), 677-679. doi:10.1016/s0042-207x(97)00067-5
NLM
Mansano RD, Verdonck PB, Maciel HS. Mechanisms of surface roughness induced in silicon by fluorine containing plasmas [Internet]. Vaccum. 1997 ; 48( 7-9): 677-679.[citado 2024 set. 09 ] Available from: https://doi.org/10.1016/s0042-207x(97)00067-5
Vancouver
Mansano RD, Verdonck PB, Maciel HS. Mechanisms of surface roughness induced in silicon by fluorine containing plasmas [Internet]. Vaccum. 1997 ; 48( 7-9): 677-679.[citado 2024 set. 09 ] Available from: https://doi.org/10.1016/s0042-207x(97)00067-5

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