Reducing Soft Error Rate of SoCs Analog-to-Digital Interfaces With Design Diversity Redundancy (2020)
- Authors:
- USP affiliated authors: ADDED, NEMITALA - IF ; MEDINA, NILBERTO HEDER - IF ; MACCHIONE, EDUARDO LUIZ AUGUSTO - IF ; AGUIAR, VITOR ÂNGELO PAULINO DE - IF
- Unidade: IF
- DOI: 10.1109/TNS.2019.2952775
- Assunto: ÍONS PESADOS
- Agências de fomento:
- Language: Inglês
- Imprenta:
- Publisher place: Piscataway, NJ
- Date published: 2020
- Source:
- Título: IEEE Transactions on Nuclear Science
- Volume/Número/Paginação/Ano: v.. 67, n. 3, p. 518-524, 2020
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
GONZÁLEZ, Carlos J et al. Reducing Soft Error Rate of SoCs Analog-to-Digital Interfaces With Design Diversity Redundancy. IEEE Transactions on Nuclear Science, v. . 67, n. 3, p. 518-524, 2020Tradução . . Disponível em: https://doi.org/10.1109/TNS.2019.2952775. Acesso em: 11 fev. 2026. -
APA
González, C. J., Added, N., Macchione, E. L. A., Aguiar, V. Â. P. de, Kastensmidt, F. G. L., Puchner, H. K., et al. (2020). Reducing Soft Error Rate of SoCs Analog-to-Digital Interfaces With Design Diversity Redundancy. IEEE Transactions on Nuclear Science, . 67( 3), 518-524. doi:10.1109/TNS.2019.2952775 -
NLM
González CJ, Added N, Macchione ELA, Aguiar VÂP de, Kastensmidt FGL, Puchner HK, Guazzelli MA, Medina NH, Balen TR. Reducing Soft Error Rate of SoCs Analog-to-Digital Interfaces With Design Diversity Redundancy [Internet]. IEEE Transactions on Nuclear Science. 2020 ;. 67( 3): 518-524.[citado 2026 fev. 11 ] Available from: https://doi.org/10.1109/TNS.2019.2952775 -
Vancouver
González CJ, Added N, Macchione ELA, Aguiar VÂP de, Kastensmidt FGL, Puchner HK, Guazzelli MA, Medina NH, Balen TR. Reducing Soft Error Rate of SoCs Analog-to-Digital Interfaces With Design Diversity Redundancy [Internet]. IEEE Transactions on Nuclear Science. 2020 ;. 67( 3): 518-524.[citado 2026 fev. 11 ] Available from: https://doi.org/10.1109/TNS.2019.2952775 - Heavy Ions Testing of an All-Convolutional Neural Network for Image Classification Evolved by Genetic Algorithms and Implemented on SRAM-Based FPGA
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Informações sobre o DOI: 10.1109/TNS.2019.2952775 (Fonte: oaDOI API)
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