Sidewall angle influence on the finFET analog parameters (2007)
- Authors:
- USP affiliated authors: MARTINO, JOAO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Publisher place: Pennington
- Date published: 2007
- Source:
- Título do periódico: SBMicro 2007
- ISSN: 1938-5862
- Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO
-
ABNT
GIACOMINI, Renato Camargo e MARTINO, João Antonio e PAVANELLO, Marcelo Antonio. Sidewall angle influence on the finFET analog parameters. 2007, Anais.. Pennington: The Electrochemical Society, 2007. . Acesso em: 28 mar. 2024. -
APA
Giacomini, R. C., Martino, J. A., & Pavanello, M. A. (2007). Sidewall angle influence on the finFET analog parameters. In SBMicro 2007. Pennington: The Electrochemical Society. -
NLM
Giacomini RC, Martino JA, Pavanello MA. Sidewall angle influence on the finFET analog parameters. SBMicro 2007. 2007 ;[citado 2024 mar. 28 ] -
Vancouver
Giacomini RC, Martino JA, Pavanello MA. Sidewall angle influence on the finFET analog parameters. SBMicro 2007. 2007 ;[citado 2024 mar. 28 ] - Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range
- Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures
- Comparison between conventional and graded-channel SOI nMOSFETs in low temperature operation
- Analog performance of graded-channel SOI NMOSFETS at low temperatures
- Impact of the graded-channel architecture on double gate transistors for high-performance analog applications
- Analysis of deep submicrometer bulk and fully depleted soi nmosfet analog operation at cryogenic temperatures
- Physical characterization and reliability aspects of MuGFETs
- A study on the self-heating effect in deep-submicrometer partially depleted SOI MOSFETs at low temperatures
- Halo effect on 0.13 'mu'm floating-body partially depleted SOI n-Mosfets in low temperature operation
- Analog circuit design using graded-channel silicon-on-insulator nMOSFETs
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