Sidewall angle influence on the finFET analog parameters (2007)
- Authors:
- USP affiliated authors: MARTINO, JOAO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Publisher place: Pennington
- Date published: 2007
- Source:
- Título: SBMicro 2007
- ISSN: 1938-5862
- Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO
-
ABNT
GIACOMINI, Renato Camargo e MARTINO, João Antonio e PAVANELLO, Marcelo Antonio. Sidewall angle influence on the finFET analog parameters. 2007, Anais.. Pennington: The Electrochemical Society, 2007. . Acesso em: 20 jan. 2026. -
APA
Giacomini, R. C., Martino, J. A., & Pavanello, M. A. (2007). Sidewall angle influence on the finFET analog parameters. In SBMicro 2007. Pennington: The Electrochemical Society. -
NLM
Giacomini RC, Martino JA, Pavanello MA. Sidewall angle influence on the finFET analog parameters. SBMicro 2007. 2007 ;[citado 2026 jan. 20 ] -
Vancouver
Giacomini RC, Martino JA, Pavanello MA. Sidewall angle influence on the finFET analog parameters. SBMicro 2007. 2007 ;[citado 2026 jan. 20 ] - A simple analytical model of graded-channel SOI nMOSFET transconductance
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
- Implementation of high performance operational transconductance amplifiers using graded-channel SOI nMOSFETs
- Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures
- Low temperature operation of undoped body triple-gate finFETs from an analog perspective
- Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs
- Behavior of graded-channel fully depleted SOI NMOSFET at high temperatures
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