Implementation of high performance operational transconductance amplifiers using graded-channel SOI nMOSFETs (2005)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Publisher place: Pennington
- Date published: 2005
- Source:
- Conference titles: International Symposium on Silicon-on-Insulator Technology and Devices
-
ABNT
GIMENEZ, Salvador Pinillos et al. Implementation of high performance operational transconductance amplifiers using graded-channel SOI nMOSFETs. International Symposium on Silicon-on-Insulator Technology and Devices XII: proceedings. Tradução . Pennington: The Electrochemical Society, 2005. . . Acesso em: 11 mar. 2026. -
APA
Gimenez, S. P., Pavanello, M. A., Martino, J. A., & Flandre, D. (2005). Implementation of high performance operational transconductance amplifiers using graded-channel SOI nMOSFETs. In International Symposium on Silicon-on-Insulator Technology and Devices XII: proceedings. Pennington: The Electrochemical Society. -
NLM
Gimenez SP, Pavanello MA, Martino JA, Flandre D. Implementation of high performance operational transconductance amplifiers using graded-channel SOI nMOSFETs. In: International Symposium on Silicon-on-Insulator Technology and Devices XII: proceedings. Pennington: The Electrochemical Society; 2005. [citado 2026 mar. 11 ] -
Vancouver
Gimenez SP, Pavanello MA, Martino JA, Flandre D. Implementation of high performance operational transconductance amplifiers using graded-channel SOI nMOSFETs. In: International Symposium on Silicon-on-Insulator Technology and Devices XII: proceedings. Pennington: The Electrochemical Society; 2005. [citado 2026 mar. 11 ] - Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs
- Analysis on GC SOI MOSFET analog parameters at high temperatures
- Operation of double gate graded-channel transistors at low temperatures
- Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature
- Analog performance of graded-channel SOI NMOSFETS at low temperatures
- A simple analytical model of graded-channel SOI nMOSFET transconductance
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
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