Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape (2009)
- Autores:
- Autores USP: MARTINO, JOAO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- DOI: 10.1088/0268-1242/24/11/115017
- Assunto: MICROELETRÔNICA
- Idioma: Inglês
- Imprenta:
- Local: Bristol; Woodbury
- Data de publicação: 2009
- Fonte:
- Título do periódico: Semiconductor Science and Technology
- ISSN: 0268-1242
- Volume/Número/Paginação/Ano: v. 24, n.11, 2009
- Este periódico é de assinatura
- Este artigo NÃO é de acesso aberto
- Cor do Acesso Aberto: closed
-
ABNT
BÜHLER, Rudolf Theoderich et al. Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape. Semiconductor Science and Technology, v. 24, n. 11, 2009Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/24/11/115017. Acesso em: 19 set. 2024. -
APA
Bühler, R. T., Giacomini, R., Pavanello, M. A., & Martino, J. A. (2009). Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape. Semiconductor Science and Technology, 24( 11). doi:10.1088/0268-1242/24/11/115017 -
NLM
Bühler RT, Giacomini R, Pavanello MA, Martino JA. Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape [Internet]. Semiconductor Science and Technology. 2009 ; 24( 11):[citado 2024 set. 19 ] Available from: https://doi.org/10.1088/0268-1242/24/11/115017 -
Vancouver
Bühler RT, Giacomini R, Pavanello MA, Martino JA. Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape [Internet]. Semiconductor Science and Technology. 2009 ; 24( 11):[citado 2024 set. 19 ] Available from: https://doi.org/10.1088/0268-1242/24/11/115017 - Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range
- Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures
- Comparison between conventional and graded-channel SOI nMOSFETs in low temperature operation
- Analog performance of graded-channel SOI NMOSFETS at low temperatures
- Impact of the graded-channel architecture on double gate transistors for high-performance analog applications
- Comparison between 0.13Mm partially-depleted silicon-on-insulator technology with floating body operation at 300 K and 90 K
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
Informações sobre o DOI: 10.1088/0268-1242/24/11/115017 (Fonte: oaDOI API)
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