Analysis of deep submicrometer bulk and fully depleted soi nmosfet analog operation at cryogenic temperatures (2005)
- Autores:
- Autores USP: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- Assuntos: MICROELETRÔNICA; CIRCUITOS INTEGRADOS
- Idioma: Inglês
- Imprenta:
- Editora: The Electrochemical Society
- Local: Pennington
- Data de publicação: 2005
- Fonte:
- Nome do evento: International Symposium on Silicon-on-Insulator Technology and Devices
-
ABNT
PAVANELLO, Marcelo Antonio et al. Analysis of deep submicrometer bulk and fully depleted soi nmosfet analog operation at cryogenic temperatures. International Symposium on Silicon-on-Insulator Technology and Devices XII: proceedings. Tradução . Pennington: The Electrochemical Society, 2005. . . Acesso em: 26 abr. 2024. -
APA
Pavanello, M. A., Martino, J. A., Simoen, E., & Claeys, C. (2005). Analysis of deep submicrometer bulk and fully depleted soi nmosfet analog operation at cryogenic temperatures. In International Symposium on Silicon-on-Insulator Technology and Devices XII: proceedings. Pennington: The Electrochemical Society. -
NLM
Pavanello MA, Martino JA, Simoen E, Claeys C. Analysis of deep submicrometer bulk and fully depleted soi nmosfet analog operation at cryogenic temperatures. In: International Symposium on Silicon-on-Insulator Technology and Devices XII: proceedings. Pennington: The Electrochemical Society; 2005. [citado 2024 abr. 26 ] -
Vancouver
Pavanello MA, Martino JA, Simoen E, Claeys C. Analysis of deep submicrometer bulk and fully depleted soi nmosfet analog operation at cryogenic temperatures. In: International Symposium on Silicon-on-Insulator Technology and Devices XII: proceedings. Pennington: The Electrochemical Society; 2005. [citado 2024 abr. 26 ] - Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range
- Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures
- Comparison between conventional and graded-channel SOI nMOSFETs in low temperature operation
- Analog performance of graded-channel SOI NMOSFETS at low temperatures
- Impact of the graded-channel architecture on double gate transistors for high-performance analog applications
- Comparison between 0.13Mm partially-depleted silicon-on-insulator technology with floating body operation at 300 K and 90 K
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
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