ReP USP - Resultado da busca

Artigo de periodico
Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor (2005)
Cerdeira, Antonio ; Alemán, Miguel A.; Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis ; Vancaillie, Laurent
Source: IEEE Transactions on Electron Devices. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
CERDEIRA, Antonio et al. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor. IEEE Transactions on Electron Devices, v. 52, n. 5, p. 967-972, 2005Tradução . . Disponível em: https://doi.org/10.1109/ted.2005.846327. Acesso em: 16 nov. 2025.
APA
Cerdeira, A., Alemán, M. A., Pavanello, M. A., Martino, J. A., Flandre, D., & Vancaillie, L. (2005). Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor. IEEE Transactions on Electron Devices, 52( 5), 967-972. doi:10.1109/ted.2005.846327
NLM
Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Flandre D, Vancaillie L. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor [Internet]. IEEE Transactions on Electron Devices. 2005 ;52( 5): 967-972.[citado 2025 nov. 16 ] Available from: https://doi.org/10.1109/ted.2005.846327
Vancouver
Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Flandre D, Vancaillie L. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor [Internet]. IEEE Transactions on Electron Devices. 2005 ;52( 5): 967-972.[citado 2025 nov. 16 ] Available from: https://doi.org/10.1109/ted.2005.846327
Artigo de periodico
SOI technology characterization using SOI-MOS capacitor (2005)
Sonnenberg, Victor ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SONNENBERG, Victor e MARTINO, João Antonio. SOI technology characterization using SOI-MOS capacitor. Solid-State Electronics, 2005Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2004.06.010. Acesso em: 16 nov. 2025.
APA
Sonnenberg, V., & Martino, J. A. (2005). SOI technology characterization using SOI-MOS capacitor. Solid-State Electronics. doi:10.1016/j.sse.2004.06.010
NLM
Sonnenberg V, Martino JA. SOI technology characterization using SOI-MOS capacitor [Internet]. Solid-State Electronics. 2005 ;[citado 2025 nov. 16 ] Available from: https://doi.org/10.1016/j.sse.2004.06.010
Vancouver
Sonnenberg V, Martino JA. SOI technology characterization using SOI-MOS capacitor [Internet]. Solid-State Electronics. 2005 ;[citado 2025 nov. 16 ] Available from: https://doi.org/10.1016/j.sse.2004.06.010
Artigo de periodico
An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Dessard, Vincent; Flandre, Denis
Source: Electrochemical and Solid-State Letters. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics. Electrochemical and Solid-State Letters, v. 3, n. Ja 2000, p. 50-52, 2000Tradução . . Disponível em: https://doi.org/10.1149/1.1390955. Acesso em: 16 nov. 2025.
APA
Pavanello, M. A., Martino, J. A., Dessard, V., & Flandre, D. (2000). An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics. Electrochemical and Solid-State Letters, 3( Ja 2000), 50-52. doi:10.1149/1.1390955
NLM
Pavanello MA, Martino JA, Dessard V, Flandre D. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics [Internet]. Electrochemical and Solid-State Letters. 2000 ; 3( Ja 2000): 50-52.[citado 2025 nov. 16 ] Available from: https://doi.org/10.1149/1.1390955
Vancouver
Pavanello MA, Martino JA, Dessard V, Flandre D. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics [Internet]. Electrochemical and Solid-State Letters. 2000 ; 3( Ja 2000): 50-52.[citado 2025 nov. 16 ] Available from: https://doi.org/10.1149/1.1390955
Artigo de periodico
Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction (1999)
Sonnenberg, Victor ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SONNENBERG, Victor e MARTINO, João Antonio. Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction. Solid-State Electronics, 1999Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(99)00191-4. Acesso em: 16 nov. 2025.
APA
Sonnenberg, V., & Martino, J. A. (1999). Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction. Solid-State Electronics. doi:10.1016/s0038-1101(99)00191-4
NLM
Sonnenberg V, Martino JA. Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction [Internet]. Solid-State Electronics. 1999 ;[citado 2025 nov. 16 ] Available from: https://doi.org/10.1016/s0038-1101(99)00191-4
Vancouver
Sonnenberg V, Martino JA. Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction [Internet]. Solid-State Electronics. 1999 ;[citado 2025 nov. 16 ] Available from: https://doi.org/10.1016/s0038-1101(99)00191-4
Artigo de periodico
A simple method for minimizing the transient effect in SOI nMOSFETs at low temperature (1999)
Sonnenberg, Victor ; Martino, João Antonio
Source: Electrochemical and Solid-State Letters. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SONNENBERG, Victor e MARTINO, João Antonio. A simple method for minimizing the transient effect in SOI nMOSFETs at low temperature. Electrochemical and Solid-State Letters, v. 2, n. 11, p. 585-586, 1999Tradução . . Acesso em: 16 nov. 2025.
APA
Sonnenberg, V., & Martino, J. A. (1999). A simple method for minimizing the transient effect in SOI nMOSFETs at low temperature. Electrochemical and Solid-State Letters, 2( 11), 585-586.
NLM
Sonnenberg V, Martino JA. A simple method for minimizing the transient effect in SOI nMOSFETs at low temperature. Electrochemical and Solid-State Letters. 1999 ;2( 11): 585-586.[citado 2025 nov. 16 ]
Vancouver
Sonnenberg V, Martino JA. A simple method for minimizing the transient effect in SOI nMOSFETs at low temperature. Electrochemical and Solid-State Letters. 1999 ;2( 11): 585-586.[citado 2025 nov. 16 ]
Artigo de periodico
Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's (1999)
Pavanello, Marcelo Antonio ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's. Solid-State Electronics, 1999Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(99)00178-1. Acesso em: 16 nov. 2025.
APA
Pavanello, M. A., & Martino, J. A. (1999). Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's. Solid-State Electronics. doi:10.1016/s0038-1101(99)00178-1
NLM
Pavanello MA, Martino JA. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's [Internet]. Solid-State Electronics. 1999 ;[citado 2025 nov. 16 ] Available from: https://doi.org/10.1016/s0038-1101(99)00178-1
Vancouver
Pavanello MA, Martino JA. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's [Internet]. Solid-State Electronics. 1999 ;[citado 2025 nov. 16 ] Available from: https://doi.org/10.1016/s0038-1101(99)00178-1

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