ReP USP - Resultado da busca

Artigo de periodico
Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures (2001)
Bellodi, Marcello; Martino, João Antonio
Fonte: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BELLODI, Marcello e MARTINO, João Antonio. Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures. Solid-State Electronics, v. 45, n. 5, p. 683-688, 2001Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(01)00099-5. Acesso em: 15 nov. 2025.
APA
Bellodi, M., & Martino, J. A. (2001). Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures. Solid-State Electronics, 45( 5), 683-688. doi:10.1016/s0038-1101(01)00099-5
NLM
Bellodi M, Martino JA. Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures [Internet]. Solid-State Electronics. 2001 ; 45( 5): 683-688.[citado 2025 nov. 15 ] Available from: https://doi.org/10.1016/s0038-1101(01)00099-5
Vancouver
Bellodi M, Martino JA. Study of the leakage drain current carriers in silicon-on-insulator MOSFETs at high temperatures [Internet]. Solid-State Electronics. 2001 ; 45( 5): 683-688.[citado 2025 nov. 15 ] Available from: https://doi.org/10.1016/s0038-1101(01)00099-5
Artigo de periodico
Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs (2000)
Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Fonte: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
NICOLETT, Aparecido Sirley et al. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs. Solid-State Electronics, v. No 2000, n. 11, p. 1961-1969, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00166-0. Acesso em: 15 nov. 2025.
APA
Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2000). Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs. Solid-State Electronics, No 2000( 11), 1961-1969. doi:10.1016/s0038-1101(00)00166-0
NLM
Nicolett AS, Martino JA, Simoen E, Claeys C. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs [Internet]. Solid-State Electronics. 2000 ; No 2000( 11): 1961-1969.[citado 2025 nov. 15 ] Available from: https://doi.org/10.1016/s0038-1101(00)00166-0
Vancouver
Nicolett AS, Martino JA, Simoen E, Claeys C. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs [Internet]. Solid-State Electronics. 2000 ; No 2000( 11): 1961-1969.[citado 2025 nov. 15 ] Available from: https://doi.org/10.1016/s0038-1101(00)00166-0
Artigo de periodico
Analog performance and application of graded-channel fully depleted SOI MOSFETs (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Dessard, Vincent; Flandre, Denis
Fonte: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Analog performance and application of graded-channel fully depleted SOI MOSFETs. Solid-State Electronics, v. 44, n. 7, p. 1219-1222, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00034-4. Acesso em: 15 nov. 2025.
APA
Pavanello, M. A., Martino, J. A., Dessard, V., & Flandre, D. (2000). Analog performance and application of graded-channel fully depleted SOI MOSFETs. Solid-State Electronics, 44( 7), 1219-1222. doi:10.1016/s0038-1101(00)00034-4
NLM
Pavanello MA, Martino JA, Dessard V, Flandre D. Analog performance and application of graded-channel fully depleted SOI MOSFETs [Internet]. Solid-State Electronics. 2000 ; 44( 7): 1219-1222.[citado 2025 nov. 15 ] Available from: https://doi.org/10.1016/s0038-1101(00)00034-4
Vancouver
Pavanello MA, Martino JA, Dessard V, Flandre D. Analog performance and application of graded-channel fully depleted SOI MOSFETs [Internet]. Solid-State Electronics. 2000 ; 44( 7): 1219-1222.[citado 2025 nov. 15 ] Available from: https://doi.org/10.1016/s0038-1101(00)00034-4
Artigo de periodico
Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Fonte: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, v. 44, n. 6, p. 917-922, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00032-0. Acesso em: 15 nov. 2025.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2000). Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, 44( 6), 917-922. doi:10.1016/s0038-1101(00)00032-0
NLM
Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2025 nov. 15 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0
Vancouver
Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2025 nov. 15 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0
Artigo de periodico
Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect (2000)
Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Fonte: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
NICOLETT, Aparecido Sirley et al. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect. Solid-State Electronics, v. 44, n. 4, p. 677-684, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(99)00293-2. Acesso em: 15 nov. 2025.
APA
Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2000). Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect. Solid-State Electronics, 44( 4), 677-684. doi:10.1016/s0038-1101(99)00293-2
NLM
Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect [Internet]. Solid-State Electronics. 2000 ; 44( 4): 677-684.[citado 2025 nov. 15 ] Available from: https://doi.org/10.1016/s0038-1101(99)00293-2
Vancouver
Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect [Internet]. Solid-State Electronics. 2000 ; 44( 4): 677-684.[citado 2025 nov. 15 ] Available from: https://doi.org/10.1016/s0038-1101(99)00293-2
Artigo de periodico
Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature (1997)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Colinge, Jean-Pierre
Fonte: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature. Solid-State Electronics, v. 41, n. 9, p. 1241-1246, 1997Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(97)00071-3. Acesso em: 15 nov. 2025.
APA
Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1997). Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature. Solid-State Electronics, 41( 9), 1241-1246. doi:10.1016/s0038-1101(97)00071-3
NLM
Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature [Internet]. Solid-State Electronics. 1997 ; 41( 9): 1241-1246.[citado 2025 nov. 15 ] Available from: https://doi.org/10.1016/s0038-1101(97)00071-3
Vancouver
Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature [Internet]. Solid-State Electronics. 1997 ; 41( 9): 1241-1246.[citado 2025 nov. 15 ] Available from: https://doi.org/10.1016/s0038-1101(97)00071-3
Artigo de periodico
Substrate influences on fully depleted enhacement mode SOI MOSFETs at room temperature and 77 K (1997)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Colinge, Jean-Pierre
Fonte: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Substrate influences on fully depleted enhacement mode SOI MOSFETs at room temperature and 77 K. Solid-State Electronics, v. 41, n. ja 1997, p. 111-119, 1997Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(96)00126-8. Acesso em: 15 nov. 2025.
APA
Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1997). Substrate influences on fully depleted enhacement mode SOI MOSFETs at room temperature and 77 K. Solid-State Electronics, 41( ja 1997), 111-119. doi:10.1016/s0038-1101(96)00126-8
NLM
Pavanello MA, Martino JA, Colinge J-P. Substrate influences on fully depleted enhacement mode SOI MOSFETs at room temperature and 77 K [Internet]. Solid-State Electronics. 1997 ; 41( ja 1997): 111-119.[citado 2025 nov. 15 ] Available from: https://doi.org/10.1016/s0038-1101(96)00126-8
Vancouver
Pavanello MA, Martino JA, Colinge J-P. Substrate influences on fully depleted enhacement mode SOI MOSFETs at room temperature and 77 K [Internet]. Solid-State Electronics. 1997 ; 41( ja 1997): 111-119.[citado 2025 nov. 15 ] Available from: https://doi.org/10.1016/s0038-1101(96)00126-8
Artigo de periodico
New method for determining the front and back interface trap densities of accumulation mode soi mofets at 77k (1995)
Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Fonte: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MARTINO, João Antonio e SIMOEN, Eddy e CLAEYS, Cor. New method for determining the front and back interface trap densities of accumulation mode soi mofets at 77k. Solid-State Electronics, v. 38, n. 10, p. 1799-803, 1995Tradução . . Acesso em: 15 nov. 2025.
APA
Martino, J. A., Simoen, E., & Claeys, C. (1995). New method for determining the front and back interface trap densities of accumulation mode soi mofets at 77k. Solid-State Electronics, 38( 10), 1799-803.
NLM
Martino JA, Simoen E, Claeys C. New method for determining the front and back interface trap densities of accumulation mode soi mofets at 77k. Solid-State Electronics. 1995 ;38( 10): 1799-803.[citado 2025 nov. 15 ]
Vancouver
Martino JA, Simoen E, Claeys C. New method for determining the front and back interface trap densities of accumulation mode soi mofets at 77k. Solid-State Electronics. 1995 ;38( 10): 1799-803.[citado 2025 nov. 15 ]

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