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Artigo de periodico
Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures (2016)
Oliveira, Alberto Vinicius de; Collaert, Nadine ; Thean, Aaron; Claeys, Cor ; Simoen, Eddy ; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Subjects: SEMICONDUTORES, MICROELETRÔNICA
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ABNT
OLIVEIRA, Alberto Vinicius de et al. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures. Solid-State Electronics, v. 123, p. 124-129, 2016Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2016.05.004. Acesso em: 09 out. 2024.
APA
Oliveira, A. V. de, Collaert, N., Thean, A., Claeys, C., Simoen, E., Agopian, P. G. D., & Martino, J. A. (2016). Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures. Solid-State Electronics, 123, 124-129. doi:10.1016/j.sse.2016.05.004
NLM
Oliveira AV de, Collaert N, Thean A, Claeys C, Simoen E, Agopian PGD, Martino JA. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures [Internet]. Solid-State Electronics. 2016 ; 123 124-129.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/j.sse.2016.05.004
Vancouver
Oliveira AV de, Collaert N, Thean A, Claeys C, Simoen E, Agopian PGD, Martino JA. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures [Internet]. Solid-State Electronics. 2016 ; 123 124-129.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/j.sse.2016.05.004
Artigo de periodico
Enhanced dynamic threshold voltage UTBB SOI nMOSFETs (2015)
Sasaki, Kátia Regina Akemi; Manini, Matheus Barros; Claeys, Cor ; Simoen, Eddy ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Subjects: SEMICONDUTORES, MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SASAKI, Kátia Regina Akemi et al. Enhanced dynamic threshold voltage UTBB SOI nMOSFETs. Solid-State Electronics, v. 112, p. 19-23, 2015Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2015.02.011. Acesso em: 09 out. 2024.
APA
Sasaki, K. R. A., Manini, M. B., Claeys, C., Simoen, E., & Martino, J. A. (2015). Enhanced dynamic threshold voltage UTBB SOI nMOSFETs. Solid-State Electronics, 112, 19-23. doi:10.1016/j.sse.2015.02.011
NLM
Sasaki KRA, Manini MB, Claeys C, Simoen E, Martino JA. Enhanced dynamic threshold voltage UTBB SOI nMOSFETs [Internet]. Solid-State Electronics. 2015 ; 112 19-23.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/j.sse.2015.02.011
Vancouver
Sasaki KRA, Manini MB, Claeys C, Simoen E, Martino JA. Enhanced dynamic threshold voltage UTBB SOI nMOSFETs [Internet]. Solid-State Electronics. 2015 ; 112 19-23.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/j.sse.2015.02.011
Artigo de periodico
Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs (2015)
Bühler, Rudolf Theoderich; Agopian, Paula Ghedini Der ; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BÜHLER, Rudolf Theoderich et al. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs. Solid-State Electronics, v. 103, p. 209-215, 2015Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2014.07.010. Acesso em: 09 out. 2024.
APA
Bühler, R. T., Agopian, P. G. D., Collaert, N., Simoen, E., Claeys, C., & Martino, J. A. (2015). Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs. Solid-State Electronics, 103, 209-215. doi:10.1016/j.sse.2014.07.010
NLM
Bühler RT, Agopian PGD, Collaert N, Simoen E, Claeys C, Martino JA. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs [Internet]. Solid-State Electronics. 2015 ;103 209-215.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/j.sse.2014.07.010
Vancouver
Bühler RT, Agopian PGD, Collaert N, Simoen E, Claeys C, Martino JA. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs [Internet]. Solid-State Electronics. 2015 ;103 209-215.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/j.sse.2014.07.010
Artigo de periodico
Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism (2015)
Martino, Márcio Dalla Valle; Thean, Aaron; Claeys, Cor ; Neves, Felipe S; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Vandooren, A; Rooyackers, Rita; Simoen, Eddy
Source: Solid-State Electronics. Unidade: EP
Subjects: TRANSISTORES, MICROELETRÔNICA
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ABNT
MARTINO, Márcio Dalla Valle et al. Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism. Solid-State Electronics, v. 112, p. 51-55, 2015Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2015.02.006. Acesso em: 09 out. 2024.
APA
Martino, M. D. V., Thean, A., Claeys, C., Neves, F. S., Agopian, P. G. D., Martino, J. A., et al. (2015). Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism. Solid-State Electronics, 112, 51-55. doi:10.1016/j.sse.2015.02.006
NLM
Martino MDV, Thean A, Claeys C, Neves FS, Agopian PGD, Martino JA, Vandooren A, Rooyackers R, Simoen E. Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism [Internet]. Solid-State Electronics. 2015 ; 112 51-55.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/j.sse.2015.02.006
Vancouver
Martino MDV, Thean A, Claeys C, Neves FS, Agopian PGD, Martino JA, Vandooren A, Rooyackers R, Simoen E. Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism [Internet]. Solid-State Electronics. 2015 ; 112 51-55.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/j.sse.2015.02.006
Artigo de periodico
Threshold voltage extraction in Tunnel FETs (2014)
Ortiz-Conde, Adelmo; Martino, João Antonio ; Garcia- Sanchez, Francisco J.; Muci, Juan; Martino, João Antonio ; Agopian, Paula Ghedini Der ; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ORTIZ-CONDE, Adelmo et al. Threshold voltage extraction in Tunnel FETs. Solid-State Electronics, v. 93, p. 49-55, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2013.12.010. Acesso em: 09 out. 2024.
APA
Ortiz-Conde, A., Martino, J. A., Garcia- Sanchez, F. J., Muci, J., Martino, J. A., Agopian, P. G. D., & Claeys, C. (2014). Threshold voltage extraction in Tunnel FETs. Solid-State Electronics, 93, 49-55. doi:10.1016/j.sse.2013.12.010
NLM
Ortiz-Conde A, Martino JA, Garcia- Sanchez FJ, Muci J, Martino JA, Agopian PGD, Claeys C. Threshold voltage extraction in Tunnel FETs [Internet]. Solid-State Electronics. 2014 ; 93 49-55.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/j.sse.2013.12.010
Vancouver
Ortiz-Conde A, Martino JA, Garcia- Sanchez FJ, Muci J, Martino JA, Agopian PGD, Claeys C. Threshold voltage extraction in Tunnel FETs [Internet]. Solid-State Electronics. 2014 ; 93 49-55.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/j.sse.2013.12.010
Artigo de periodico
Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation (2014)
Nicoletti, Talitha; Santos, Sara Dereste dos; Martino, João Antonio ; Aoulaiche, Marc; Veloso, Anabela; Claeys, Cor ; Simoen, Eddy ; Jurczak, Malgorzata
Source: Solid-State Electronics. Unidade: EP
Subjects: TEMPERATURA, MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
NICOLETTI, Talitha et al. Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation. Solid-State Electronics, v. 91, p. 53-58, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2013.09.012. Acesso em: 09 out. 2024.
APA
Nicoletti, T., Santos, S. D. dos, Martino, J. A., Aoulaiche, M., Veloso, A., Claeys, C., et al. (2014). Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation. Solid-State Electronics, 91, 53-58. doi:10.1016/j.sse.2013.09.012
NLM
Nicoletti T, Santos SD dos, Martino JA, Aoulaiche M, Veloso A, Claeys C, Simoen E, Jurczak M. Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation [Internet]. Solid-State Electronics. 2014 ; 91 53-58.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/j.sse.2013.09.012
Vancouver
Nicoletti T, Santos SD dos, Martino JA, Aoulaiche M, Veloso A, Claeys C, Simoen E, Jurczak M. Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation [Internet]. Solid-State Electronics. 2014 ; 91 53-58.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/j.sse.2013.09.012
Artigo de periodico
Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics (2014)
Santos, Sara Dereste dos; Martino, João Antonio ; Cretu, B; Strobel, V; Routoure, J.-M; Carin, R; Aoulaiche, Marc; Jurczak, Malgorzata; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Subjects: TEMPERATURA, MICROELETRÔNICA, SILÍCIO
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SANTOS, Sara Dereste dos et al. Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics. Solid-State Electronics, v. 97, p. 14-22, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2014.04.034. Acesso em: 09 out. 2024.
APA
Santos, S. D. dos, Martino, J. A., Cretu, B., Strobel, V., Routoure, J. -M., Carin, R., et al. (2014). Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics. Solid-State Electronics, 97, 14-22. doi:10.1016/j.sse.2014.04.034
NLM
Santos SD dos, Martino JA, Cretu B, Strobel V, Routoure J-M, Carin R, Aoulaiche M, Jurczak M, Claeys C. Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics [Internet]. Solid-State Electronics. 2014 ; 97 14-22.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/j.sse.2014.04.034
Vancouver
Santos SD dos, Martino JA, Cretu B, Strobel V, Routoure J-M, Carin R, Aoulaiche M, Jurczak M, Claeys C. Low-frequency noise assessment in advanced UTBOX SOI nMOSFETs with different gate dielectrics [Internet]. Solid-State Electronics. 2014 ; 97 14-22.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/j.sse.2014.04.034

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