ReP USP - Resultado da busca

Trabalho de evento
A simple model for a new SOI MOSFET with asymmetric trapezoidal gate (2003)
Giacomini, Renato Camargo; Martino, João Antonio
Source: Proceedings. Conference titles: Workshop IBERSHIP. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
GIACOMINI, Renato Camargo e MARTINO, João Antonio. A simple model for a new SOI MOSFET with asymmetric trapezoidal gate. 2003, Anais.. Havana: Escola Politécnica, Universidade de São Paulo, 2003. . Acesso em: 11 nov. 2024.
APA
Giacomini, R. C., & Martino, J. A. (2003). A simple model for a new SOI MOSFET with asymmetric trapezoidal gate. In Proceedings. Havana: Escola Politécnica, Universidade de São Paulo.
NLM
Giacomini RC, Martino JA. A simple model for a new SOI MOSFET with asymmetric trapezoidal gate. Proceedings. 2003 ;[citado 2024 nov. 11 ]
Vancouver
Giacomini RC, Martino JA. A simple model for a new SOI MOSFET with asymmetric trapezoidal gate. Proceedings. 2003 ;[citado 2024 nov. 11 ]
Trabalho de evento
Operation of double gate grated-channel transistors at low temperatures (2003)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Chung, Tae Mo; Kranti, A.; Raskin, Jean-Pierre; Flandre, Denis
Source: Proceedings. Conference titles: International Symposium on Low Temperature Electronics. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Operation of double gate grated-channel transistors at low temperatures. 2003, Anais.. Pennington: The Electrochemical Society, 2003. . Acesso em: 11 nov. 2024.
APA
Pavanello, M. A., Martino, J. A., Chung, T. M., Kranti, A., Raskin, J. -P., & Flandre, D. (2003). Operation of double gate grated-channel transistors at low temperatures. In Proceedings. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Martino JA, Chung TM, Kranti A, Raskin J-P, Flandre D. Operation of double gate grated-channel transistors at low temperatures. Proceedings. 2003 ;[citado 2024 nov. 11 ]
Vancouver
Pavanello MA, Martino JA, Chung TM, Kranti A, Raskin J-P, Flandre D. Operation of double gate grated-channel transistors at low temperatures. Proceedings. 2003 ;[citado 2024 nov. 11 ]
Trabalho de evento
Halo effect on 0.13 'mu'm floating-body partially depleted SOI n-Mosfets in low temperature operation (2003)
Martino, João Antonio ; Pavanello, Marcelo Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Proceedings. Conference titles: International Symposium on Low Temperature Electronics. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MARTINO, João Antonio et al. Halo effect on 0.13 'mu'm floating-body partially depleted SOI n-Mosfets in low temperature operation. 2003, Anais.. Pennington: The Electrochemical Society, 2003. . Acesso em: 11 nov. 2024.
APA
Martino, J. A., Pavanello, M. A., Simoen, E., & Claeys, C. (2003). Halo effect on 0.13 'mu'm floating-body partially depleted SOI n-Mosfets in low temperature operation. In Proceedings. Pennington: The Electrochemical Society.
NLM
Martino JA, Pavanello MA, Simoen E, Claeys C. Halo effect on 0.13 'mu'm floating-body partially depleted SOI n-Mosfets in low temperature operation. Proceedings. 2003 ;[citado 2024 nov. 11 ]
Vancouver
Martino JA, Pavanello MA, Simoen E, Claeys C. Halo effect on 0.13 'mu'm floating-body partially depleted SOI n-Mosfets in low temperature operation. Proceedings. 2003 ;[citado 2024 nov. 11 ]
Trabalho de evento
Extraction of the oxide charge density at front and back interfaces of SOI NMOSFET devices (2001)
Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Proceedings. Conference titles: International Symposium on Silicon-on-Insulator Technology and Devices. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
NICOLETT, Aparecido Sirley et al. Extraction of the oxide charge density at front and back interfaces of SOI NMOSFET devices. 2001, Anais.. Pennington: The Electrochemical Society, 2001. . Acesso em: 11 nov. 2024.
APA
Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2001). Extraction of the oxide charge density at front and back interfaces of SOI NMOSFET devices. In Proceedings. Pennington: The Electrochemical Society.
NLM
Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the oxide charge density at front and back interfaces of SOI NMOSFET devices. Proceedings. 2001 ;[citado 2024 nov. 11 ]
Vancouver
Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the oxide charge density at front and back interfaces of SOI NMOSFET devices. Proceedings. 2001 ;[citado 2024 nov. 11 ]
Trabalho de evento
Analog circuit design using graded-channel SOI NMOSFETs (2001)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: Proceedings. Conference titles: Symposium on Integrated Circuits and Systems Design. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Analog circuit design using graded-channel SOI NMOSFETs. 2001, Anais.. Piscataway: IEEE, 2001. . Acesso em: 11 nov. 2024.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2001). Analog circuit design using graded-channel SOI NMOSFETs. In Proceedings. Piscataway: IEEE.
NLM
Pavanello MA, Martino JA, Flandre D. Analog circuit design using graded-channel SOI NMOSFETs. Proceedings. 2001 ;[citado 2024 nov. 11 ]
Vancouver
Pavanello MA, Martino JA, Flandre D. Analog circuit design using graded-channel SOI NMOSFETs. Proceedings. 2001 ;[citado 2024 nov. 11 ]
Trabalho de evento
High performance current mirrors using graded-channel SOI MOSFETs (2001)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: Proceedings. Conference titles: International Symposium on Silicon-on-Insulator Technology and Devices. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. High performance current mirrors using graded-channel SOI MOSFETs. 2001, Anais.. Pennington: The Electrochemical Society, 2001. . Acesso em: 11 nov. 2024.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2001). High performance current mirrors using graded-channel SOI MOSFETs. In Proceedings. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Martino JA, Flandre D. High performance current mirrors using graded-channel SOI MOSFETs. Proceedings. 2001 ;[citado 2024 nov. 11 ]
Vancouver
Pavanello MA, Martino JA, Flandre D. High performance current mirrors using graded-channel SOI MOSFETs. Proceedings. 2001 ;[citado 2024 nov. 11 ]
Trabalho de evento
Modeling of the leakage drain current in accumulation mode SOI pMOSFETs for high-temperature applications (2001)
Bellodi, Marcello; Iniguez, Benjamin; Flandre, Denis ; Martino, João Antonio
Source: Proceedings. Conference titles: International Symposium on Silicon-on-Insulator Technology and Devices. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BELLODI, Marcello et al. Modeling of the leakage drain current in accumulation mode SOI pMOSFETs for high-temperature applications. 2001, Anais.. Pennington: The Electrochemical Society, 2001. . Acesso em: 11 nov. 2024.
APA
Bellodi, M., Iniguez, B., Flandre, D., & Martino, J. A. (2001). Modeling of the leakage drain current in accumulation mode SOI pMOSFETs for high-temperature applications. In Proceedings. Pennington: The Electrochemical Society.
NLM
Bellodi M, Iniguez B, Flandre D, Martino JA. Modeling of the leakage drain current in accumulation mode SOI pMOSFETs for high-temperature applications. Proceedings. 2001 ;[citado 2024 nov. 11 ]
Vancouver
Bellodi M, Iniguez B, Flandre D, Martino JA. Modeling of the leakage drain current in accumulation mode SOI pMOSFETs for high-temperature applications. Proceedings. 2001 ;[citado 2024 nov. 11 ]
Trabalho de evento
Determination of silicon film doping concentration and back interface oxide charge density using SOI-MOS capacitor (2001)
Sonnenberg, Victor ; Martino, João Antonio
Source: Proceedings. Conference titles: International Symposium on Silicon-on-Insulator Technology and Devices. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SONNENBERG, Victor e MARTINO, João Antonio. Determination of silicon film doping concentration and back interface oxide charge density using SOI-MOS capacitor. 2001, Anais.. Pennington: The Electrochemical Society, 2001. . Acesso em: 11 nov. 2024.
APA
Sonnenberg, V., & Martino, J. A. (2001). Determination of silicon film doping concentration and back interface oxide charge density using SOI-MOS capacitor. In Proceedings. Pennington: The Electrochemical Society.
NLM
Sonnenberg V, Martino JA. Determination of silicon film doping concentration and back interface oxide charge density using SOI-MOS capacitor. Proceedings. 2001 ;[citado 2024 nov. 11 ]
Vancouver
Sonnenberg V, Martino JA. Determination of silicon film doping concentration and back interface oxide charge density using SOI-MOS capacitor. Proceedings. 2001 ;[citado 2024 nov. 11 ]
Trabalho de evento
Comparison of floating-body effects in conventional and graded-channel fully-depleted silicon-on-insulator nMOSFETs (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: Proceedings. Conference titles: IEEE International Conference on Devices, Circuits and Syems. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Comparison of floating-body effects in conventional and graded-channel fully-depleted silicon-on-insulator nMOSFETs. 2000, Anais.. Piscataway: IEEE, 2000. . Acesso em: 11 nov. 2024.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2000). Comparison of floating-body effects in conventional and graded-channel fully-depleted silicon-on-insulator nMOSFETs. In Proceedings. Piscataway: IEEE.
NLM
Pavanello MA, Martino JA, Flandre D. Comparison of floating-body effects in conventional and graded-channel fully-depleted silicon-on-insulator nMOSFETs. Proceedings. 2000 ;[citado 2024 nov. 11 ]
Vancouver
Pavanello MA, Martino JA, Flandre D. Comparison of floating-body effects in conventional and graded-channel fully-depleted silicon-on-insulator nMOSFETs. Proceedings. 2000 ;[citado 2024 nov. 11 ]
Trabalho de evento
A new method to extract the LDD doping concentration on fully depleted SOI nMOSFET at 300 K (2000)
Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Proceedings. Conference titles: IEEE International Conference on Devices, Circuits and Syems. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
NICOLETT, Aparecido Sirley et al. A new method to extract the LDD doping concentration on fully depleted SOI nMOSFET at 300 K. 2000, Anais.. Piscataway: IEEE, 2000. . Acesso em: 11 nov. 2024.
APA
Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2000). A new method to extract the LDD doping concentration on fully depleted SOI nMOSFET at 300 K. In Proceedings. Piscataway: IEEE.
NLM
Nicolett AS, Martino JA, Simoen E, Claeys C. A new method to extract the LDD doping concentration on fully depleted SOI nMOSFET at 300 K. Proceedings. 2000 ;[citado 2024 nov. 11 ]
Vancouver
Nicolett AS, Martino JA, Simoen E, Claeys C. A new method to extract the LDD doping concentration on fully depleted SOI nMOSFET at 300 K. Proceedings. 2000 ;[citado 2024 nov. 11 ]

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