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Filtros : "Doria, Rodrigo Trevisoli" Limpar

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1 - 8 (8 records)

  • Artigo de periodico

    In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs (2015)

    Doria, Rodrigo Trevisoli ; Claeys, Cor ; Simoen, Eddy ; Souza, Marcio Alves Sodré de; Martino, João Antonio

    Source: Microelectronic Engineering. Unidade: EP

    Assunto: MICROELETRÔNICA

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    • ABNT

      DORIA, Rodrigo Trevisoli et al. In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs. Microelectronic Engineering, v. 147, n. 1, p. 92-95, 2015Tradução . . Disponível em: https://doi.org/10.1016/j.mee.2015.04.056. Acesso em: 14 nov. 2024.

    • APA

      Doria, R. T., Claeys, C., Simoen, E., Souza, M. A. S. de, & Martino, J. A. (2015). In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs. Microelectronic Engineering, 147( 1), 92-95. doi:10.1016/j.mee.2015.04.056

    • NLM

      Doria RT, Claeys C, Simoen E, Souza MAS de, Martino JA. In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs [Internet]. Microelectronic Engineering. 2015 ; 147( 1): 92-95.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1016/j.mee.2015.04.056

    • Vancouver

      Doria RT, Claeys C, Simoen E, Souza MAS de, Martino JA. In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs [Internet]. Microelectronic Engineering. 2015 ; 147( 1): 92-95.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1016/j.mee.2015.04.056

  • Artigo de periodico

    Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates (2013)

    Doria, Rodrigo Trevisoli ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor ; Pavanello, Marcelo Antonio

    Source: Solid-State Electronics. Unidade: EP

    Assunto: SILÍCIO

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    • ABNT

      DORIA, Rodrigo Trevisoli et al. Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates. Solid-State Electronics, v. 90, p. 121-126, 2013Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2013.02.042. Acesso em: 14 nov. 2024.

    • APA

      Doria, R. T., Martino, J. A., Simoen, E., Claeys, C., & Pavanello, M. A. (2013). Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates. Solid-State Electronics, 90, 121-126. doi:10.1016/j.sse.2013.02.042

    • NLM

      Doria RT, Martino JA, Simoen E, Claeys C, Pavanello MA. Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates [Internet]. Solid-State Electronics. 2013 ; 90 121-126.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1016/j.sse.2013.02.042

    • Vancouver

      Doria RT, Martino JA, Simoen E, Claeys C, Pavanello MA. Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates [Internet]. Solid-State Electronics. 2013 ; 90 121-126.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1016/j.sse.2013.02.042

  • Trabalho de evento

    Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements (2012)

    Mariniello, Genaro ; Doria, Rodrigo Trevisoli ; Trevisoli, Renan ; Souza, Michelly de ; Pavanello, Marcelo Antonio

    Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP

    Assunto: MICROELETRÔNICA

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    • ABNT

      MARINIELLO, Genaro et al. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0231ecst. Acesso em: 14 nov. 2024.

    • APA

      Mariniello, G., Doria, R. T., Trevisoli, R., Souza, M. de, & Pavanello, M. A. (2012). Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0231ecst

    • NLM

      Mariniello G, Doria RT, Trevisoli R, Souza M de, Pavanello MA. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 14 ] Available from: https://doi.org/10.1149/04901.0231ecst

    • Vancouver

      Mariniello G, Doria RT, Trevisoli R, Souza M de, Pavanello MA. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 14 ] Available from: https://doi.org/10.1149/04901.0231ecst

  • Trabalho de evento

    Comparative study of biaxial and uniaxial mechanical stress influence on the low frequency noise of fully depleted SOI nMOSFETs operating in triode and saturation regime (2012)

    Souza, Marcio Alves Sodré de; Doria, Rodrigo Trevisoli ; Souza, Michelly de ; Martino, João Antonio ; Pavanello, Marcelo Antonio

    Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP

    Assunto: MICROELETRÔNICA

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    • ABNT

      SOUZA, Marcio Alves Sodré de et al. Comparative study of biaxial and uniaxial mechanical stress influence on the low frequency noise of fully depleted SOI nMOSFETs operating in triode and saturation regime. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0077ecst. Acesso em: 14 nov. 2024.

    • APA

      Souza, M. A. S. de, Doria, R. T., Souza, M. de, Martino, J. A., & Pavanello, M. A. (2012). Comparative study of biaxial and uniaxial mechanical stress influence on the low frequency noise of fully depleted SOI nMOSFETs operating in triode and saturation regime. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0077ecst

    • NLM

      Souza MAS de, Doria RT, Souza M de, Martino JA, Pavanello MA. Comparative study of biaxial and uniaxial mechanical stress influence on the low frequency noise of fully depleted SOI nMOSFETs operating in triode and saturation regime [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 14 ] Available from: https://doi.org/10.1149/04901.0077ecst

    • Vancouver

      Souza MAS de, Doria RT, Souza M de, Martino JA, Pavanello MA. Comparative study of biaxial and uniaxial mechanical stress influence on the low frequency noise of fully depleted SOI nMOSFETs operating in triode and saturation regime [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 14 ] Available from: https://doi.org/10.1149/04901.0077ecst

  • Trabalho de evento

    Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors (2012)

    Trevisoli, Renan ; Doria, Rodrigo Trevisoli ; Souza, Michelly de ; Pavanello, Marcelo Antonio

    Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP

    Assunto: MICROELETRÔNICA

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    • ABNT

      TREVISOLI, Renan et al. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0207ecst. Acesso em: 14 nov. 2024.

    • APA

      Trevisoli, R., Doria, R. T., Souza, M. de, & Pavanello, M. A. (2012). Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0207ecst

    • NLM

      Trevisoli R, Doria RT, Souza M de, Pavanello MA. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 14 ] Available from: https://doi.org/10.1149/04901.0207ecst

    • Vancouver

      Trevisoli R, Doria RT, Souza M de, Pavanello MA. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 14 ] Available from: https://doi.org/10.1149/04901.0207ecst

  • Trabalho de evento

    Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance (2012)

    Doria, Rodrigo Trevisoli ; Trevisoli, Renan ; Souza, Michelly de ; Pavanello, Marcelo Antonio

    Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP

    Assunto: MICROELETRÔNICA

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    • ABNT

      DORIA, Rodrigo Trevisoli et al. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0215ecst. Acesso em: 14 nov. 2024.

    • APA

      Doria, R. T., Trevisoli, R., Souza, M. de, & Pavanello, M. A. (2012). Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0215ecst

    • NLM

      Doria RT, Trevisoli R, Souza M de, Pavanello MA. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 14 ] Available from: https://doi.org/10.1149/04901.0215ecst

    • Vancouver

      Doria RT, Trevisoli R, Souza M de, Pavanello MA. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 14 ] Available from: https://doi.org/10.1149/04901.0215ecst

  • Tese (Doutorado)

    Operação analógica de transistores de múltiplas portas em função da temperatura (2010)

    Doria, Rodrigo Trevisoli ; Pavanello, Marcelo Antonio (Orientador)

    Unidade: EP

    Subjects: TRANSISTORES, SILÍCIO, DISPOSITIVOS ELETRÔNICOS, CIRCUITOS ANALÓGICOS

    Acesso à fonteHow to cite
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    • ABNT

      DORIA, Rodrigo Trevisoli. Operação analógica de transistores de múltiplas portas em função da temperatura. 2010. Tese (Doutorado) – Universidade de São Paulo, São Paulo, 2010. Disponível em: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10012011-135500/. Acesso em: 14 nov. 2024.

    • APA

      Doria, R. T. (2010). Operação analógica de transistores de múltiplas portas em função da temperatura (Tese (Doutorado). Universidade de São Paulo, São Paulo. Recuperado de http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10012011-135500/

    • NLM

      Doria RT. Operação analógica de transistores de múltiplas portas em função da temperatura [Internet]. 2010 ;[citado 2024 nov. 14 ] Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10012011-135500/

    • Vancouver

      Doria RT. Operação analógica de transistores de múltiplas portas em função da temperatura [Internet]. 2010 ;[citado 2024 nov. 14 ] Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10012011-135500/

  • Artigo de periodico

    Analog operation and harmonic distortion temperature dependence of nMOS junctionless transistors (2010)

    Doria, Rodrigo Trevisoli ; Pavanello, Marcelo Antonio ; Lee, C. W.; Ferain, Isabelle; Akhavan, Nima Dehdashti; Yan, Ran; Razavi, Pedram; Yu, Ran; Kranti, A; Colinge, Jean-Pierre

    Source: Microelectronics Technology and Devices - SBMicro 2010. Unidade: EP

    Assunto: ELETROQUÍMICA

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    • ABNT

      DORIA, Rodrigo Trevisoli et al. Analog operation and harmonic distortion temperature dependence of nMOS junctionless transistors. Microelectronics Technology and Devices - SBMicro 2010, v. 31, n. 1, p. 13-20, 2010Tradução . . Disponível em: https://doi.org/10.1149/1.3474137. Acesso em: 14 nov. 2024.

    • APA

      Doria, R. T., Pavanello, M. A., Lee, C. W., Ferain, I., Akhavan, N. D., Yan, R., et al. (2010). Analog operation and harmonic distortion temperature dependence of nMOS junctionless transistors. Microelectronics Technology and Devices - SBMicro 2010, 31( 1), 13-20. doi:10.1149/1.3474137

    • NLM

      Doria RT, Pavanello MA, Lee CW, Ferain I, Akhavan ND, Yan R, Razavi P, Yu R, Kranti A, Colinge J-P. Analog operation and harmonic distortion temperature dependence of nMOS junctionless transistors [Internet]. Microelectronics Technology and Devices - SBMicro 2010. 2010 ;31( 1): 13-20.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1149/1.3474137

    • Vancouver

      Doria RT, Pavanello MA, Lee CW, Ferain I, Akhavan ND, Yan R, Razavi P, Yu R, Kranti A, Colinge J-P. Analog operation and harmonic distortion temperature dependence of nMOS junctionless transistors [Internet]. Microelectronics Technology and Devices - SBMicro 2010. 2010 ;31( 1): 13-20.[citado 2024 nov. 14 ] Available from: https://doi.org/10.1149/1.3474137
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