ReP USP - Resultado da busca

Trabalho de evento
On the variability of the low-frequency noise in UTBOX SOI nMOSFETs (2012)
Simoen, Eddy ; Caño de Andrade, Maria Glória ; Almeida, Luciano Mendes; Aoulaiche, Marc; Caillat, Christian; Jurczak, Malgorzata; Claeys, Cor
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SIMOEN, Eddy et al. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0051ecst. Acesso em: 12 nov. 2024.
APA
Simoen, E., Caño de Andrade, M. G., Almeida, L. M., Aoulaiche, M., Caillat, C., Jurczak, M., & Claeys, C. (2012). On the variability of the low-frequency noise in UTBOX SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0051ecst
NLM
Simoen E, Caño de Andrade MG, Almeida LM, Aoulaiche M, Caillat C, Jurczak M, Claeys C. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://doi.org/10.1149/04901.0051ecst
Vancouver
Simoen E, Caño de Andrade MG, Almeida LM, Aoulaiche M, Caillat C, Jurczak M, Claeys C. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://doi.org/10.1149/04901.0051ecst
Trabalho de evento
Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI (2012)
Caño de Andrade, Maria Glória ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
CAÑO DE ANDRADE, Maria Glória et al. Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0111ecst. Acesso em: 12 nov. 2024.
APA
Caño de Andrade, M. G., Martino, J. A., Simoen, E., & Claeys, C. (2012). Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0111ecst
NLM
Caño de Andrade MG, Martino JA, Simoen E, Claeys C. Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://doi.org/10.1149/04901.0111ecst
Vancouver
Caño de Andrade MG, Martino JA, Simoen E, Claeys C. Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://doi.org/10.1149/04901.0111ecst
Trabalho de evento
Temperature influence on nanowire tunnel field effect transistors (2012)
Neves, Felipe Souza; Martino, Márcio Dalla Valle; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Rooyackers, Rita ; Leonelli, Daniele ; Claeys, Cor
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
NEVES, Felipe Souza et al. Temperature influence on nanowire tunnel field effect transistors. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0223ecst. Acesso em: 12 nov. 2024.
APA
Neves, F. S., Martino, M. D. V., Agopian, P. G. D., Martino, J. A., Rooyackers, R., Leonelli, D., & Claeys, C. (2012). Temperature influence on nanowire tunnel field effect transistors. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0223ecst
NLM
Neves FS, Martino MDV, Agopian PGD, Martino JA, Rooyackers R, Leonelli D, Claeys C. Temperature influence on nanowire tunnel field effect transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://doi.org/10.1149/04901.0223ecst
Vancouver
Neves FS, Martino MDV, Agopian PGD, Martino JA, Rooyackers R, Leonelli D, Claeys C. Temperature influence on nanowire tunnel field effect transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://doi.org/10.1149/04901.0223ecst
Trabalho de evento
Liquid helium temperature operation of graded-channel SOI nMOSFETs (2012)
Souza, Michelly de ; Kilchytska, Valeriya ; Flandre, Denis ; Pavanello, Marcelo Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SOUZA, Michelly de et al. Liquid helium temperature operation of graded-channel SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0135ecst. Acesso em: 12 nov. 2024.
APA
Souza, M. de, Kilchytska, V., Flandre, D., & Pavanello, M. A. (2012). Liquid helium temperature operation of graded-channel SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0135ecst
NLM
Souza M de, Kilchytska V, Flandre D, Pavanello MA. Liquid helium temperature operation of graded-channel SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://doi.org/10.1149/04901.0135ecst
Vancouver
Souza M de, Kilchytska V, Flandre D, Pavanello MA. Liquid helium temperature operation of graded-channel SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://doi.org/10.1149/04901.0135ecst
Trabalho de evento
Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS (2012)
Santos, Sara Dereste dos ; Nicoletti, Talitha; Aoulaiche, Marc; Martino, João Antonio ; Veloso, A; Jurczak, Malgorzata; Simoen, Eddy ; Claeys, Cor
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SANTOS, Sara Dereste dos et al. Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf. Acesso em: 12 nov. 2024.
APA
Santos, S. D. dos, Nicoletti, T., Aoulaiche, M., Martino, J. A., Veloso, A., Jurczak, M., et al. (2012). Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. Recuperado de https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf
NLM
Santos SD dos, Nicoletti T, Aoulaiche M, Martino JA, Veloso A, Jurczak M, Simoen E, Claeys C. Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf
Vancouver
Santos SD dos, Nicoletti T, Aoulaiche M, Martino JA, Veloso A, Jurczak M, Simoen E, Claeys C. Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf
Trabalho de evento
Analysis of the silicon film thickness and the ground plane influence on ultra thin buried oxide SOI nMOSFETs. (2012)
Itocazu, Vitor Tatsuo ; Sonnenberg, Victor ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ITOCAZU, Vitor Tatsuo et al. Analysis of the silicon film thickness and the ground plane influence on ultra thin buried oxide SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0511ecst. Acesso em: 12 nov. 2024.
APA
Itocazu, V. T., Sonnenberg, V., Simoen, E., Claeys, C., & Martino, J. A. (2012). Analysis of the silicon film thickness and the ground plane influence on ultra thin buried oxide SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0511ecst
NLM
Itocazu VT, Sonnenberg V, Simoen E, Claeys C, Martino JA. Analysis of the silicon film thickness and the ground plane influence on ultra thin buried oxide SOI nMOSFETs. [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://doi.org/10.1149/04901.0511ecst
Vancouver
Itocazu VT, Sonnenberg V, Simoen E, Claeys C, Martino JA. Analysis of the silicon film thickness and the ground plane influence on ultra thin buried oxide SOI nMOSFETs. [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://doi.org/10.1149/04901.0511ecst
Trabalho de evento
Biaxial stress simulation and electrical characterization of triple-gate SOI nMOSFETs. (2012)
Bühler, Rudolf Theoderich ; Agopian, Paula Ghedini Der ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BÜHLER, Rudolf Theoderich et al. Biaxial stress simulation and electrical characterization of triple-gate SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0145ecst. Acesso em: 12 nov. 2024.
APA
Bühler, R. T., Agopian, P. G. D., Simoen, E., Claeys, C., & Martino, J. A. (2012). Biaxial stress simulation and electrical characterization of triple-gate SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0145ecst
NLM
Bühler RT, Agopian PGD, Simoen E, Claeys C, Martino JA. Biaxial stress simulation and electrical characterization of triple-gate SOI nMOSFETs. [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://doi.org/10.1149/04901.0145ecst
Vancouver
Bühler RT, Agopian PGD, Simoen E, Claeys C, Martino JA. Biaxial stress simulation and electrical characterization of triple-gate SOI nMOSFETs. [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://doi.org/10.1149/04901.0145ecst
Trabalho de evento
UTBOX SOI devices with high-k gate dielectric under analog performance (2012)
Galeti, Milene; Rodrigues, Michele; Aoulaiche, Marc; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
GALETI, Milene et al. UTBOX SOI devices with high-k gate dielectric under analog performance. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0119ecst. Acesso em: 12 nov. 2024.
APA
Galeti, M., Rodrigues, M., Aoulaiche, M., Collaert, N., Simoen, E., Claeys, C., & Martino, J. A. (2012). UTBOX SOI devices with high-k gate dielectric under analog performance. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0119ecst
NLM
Galeti M, Rodrigues M, Aoulaiche M, Collaert N, Simoen E, Claeys C, Martino JA. UTBOX SOI devices with high-k gate dielectric under analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://doi.org/10.1149/04901.0119ecst
Vancouver
Galeti M, Rodrigues M, Aoulaiche M, Collaert N, Simoen E, Claeys C, Martino JA. UTBOX SOI devices with high-k gate dielectric under analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://doi.org/10.1149/04901.0119ecst
Trabalho de evento
Hafnium aluminates deposited by atomic layer deposition: structural characterization by X-ray spectroscopy (2012)
Huanca, Danilo Roque ; Christiano, Veronica; Adelmann, Christoph; Kellerman, Guinther ; Verdonck, Patrick Bernard; Santos Filho, Sebastião Gomes dos
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
HUANCA, Danilo Roque et al. Hafnium aluminates deposited by atomic layer deposition: structural characterization by X-ray spectroscopy. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0383ecst. Acesso em: 12 nov. 2024.
APA
Huanca, D. R., Christiano, V., Adelmann, C., Kellerman, G., Verdonck, P. B., & Santos Filho, S. G. dos. (2012). Hafnium aluminates deposited by atomic layer deposition: structural characterization by X-ray spectroscopy. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0383ecst
NLM
Huanca DR, Christiano V, Adelmann C, Kellerman G, Verdonck PB, Santos Filho SG dos. Hafnium aluminates deposited by atomic layer deposition: structural characterization by X-ray spectroscopy [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://doi.org/10.1149/04901.0383ecst
Vancouver
Huanca DR, Christiano V, Adelmann C, Kellerman G, Verdonck PB, Santos Filho SG dos. Hafnium aluminates deposited by atomic layer deposition: structural characterization by X-ray spectroscopy [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 12 ] Available from: https://doi.org/10.1149/04901.0383ecst

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