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  • Fonte: Microelectronic Engineering. Unidade: EP

    Assunto: MICROELETRÔNICA

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    • ABNT

      DORIA, Rodrigo Trevisoli et al. In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs. Microelectronic Engineering, v. 147, n. 1, p. 92-95, 2015Tradução . . Disponível em: https://doi.org/10.1016/j.mee.2015.04.056. Acesso em: 16 nov. 2025.
    • APA

      Doria, R. T., Claeys, C., Simoen, E., Souza, M. A. S. de, & Martino, J. A. (2015). In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs. Microelectronic Engineering, 147( 1), 92-95. doi:10.1016/j.mee.2015.04.056
    • NLM

      Doria RT, Claeys C, Simoen E, Souza MAS de, Martino JA. In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs [Internet]. Microelectronic Engineering. 2015 ; 147( 1): 92-95.[citado 2025 nov. 16 ] Available from: https://doi.org/10.1016/j.mee.2015.04.056
    • Vancouver

      Doria RT, Claeys C, Simoen E, Souza MAS de, Martino JA. In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs [Internet]. Microelectronic Engineering. 2015 ; 147( 1): 92-95.[citado 2025 nov. 16 ] Available from: https://doi.org/10.1016/j.mee.2015.04.056
  • Fonte: Microelectronic Engineering. Unidade: EP

    Assunto: MICROELETRÔNICA

    Acesso à fonteDOIComo citar
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    • ABNT

      PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k. Microelectronic Engineering, v. 36, n. 1-4, p. 375-378, 1997Tradução . . Disponível em: https://doi.org/10.1016/s0167-9317(97)00083-x. Acesso em: 16 nov. 2025.
    • APA

      Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1997). Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k. Microelectronic Engineering, 36( 1-4), 375-378. doi:10.1016/s0167-9317(97)00083-x
    • NLM

      Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k [Internet]. Microelectronic Engineering. 1997 ; 36( 1-4): 375-378.[citado 2025 nov. 16 ] Available from: https://doi.org/10.1016/s0167-9317(97)00083-x
    • Vancouver

      Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k [Internet]. Microelectronic Engineering. 1997 ; 36( 1-4): 375-378.[citado 2025 nov. 16 ] Available from: https://doi.org/10.1016/s0167-9317(97)00083-x
  • Fonte: Microelectronic Engineering. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS

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    • ABNT

      VERDONCK, Patrick Bernard e BRASSEUR, G. e SWART, J. Reactive ion etching and plasma etching of tungsten. Microelectronic Engineering, v. 21, p. 329-332, 1993Tradução . . Disponível em: https://doi.org/10.1016/0167-9317(93)90084-i. Acesso em: 16 nov. 2025.
    • APA

      Verdonck, P. B., Brasseur, G., & Swart, J. (1993). Reactive ion etching and plasma etching of tungsten. Microelectronic Engineering, 21, 329-332. doi:10.1016/0167-9317(93)90084-i
    • NLM

      Verdonck PB, Brasseur G, Swart J. Reactive ion etching and plasma etching of tungsten [Internet]. Microelectronic Engineering. 1993 ; 21 329-332.[citado 2025 nov. 16 ] Available from: https://doi.org/10.1016/0167-9317(93)90084-i
    • Vancouver

      Verdonck PB, Brasseur G, Swart J. Reactive ion etching and plasma etching of tungsten [Internet]. Microelectronic Engineering. 1993 ; 21 329-332.[citado 2025 nov. 16 ] Available from: https://doi.org/10.1016/0167-9317(93)90084-i
  • Fonte: Microelectronic Engineering. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS

    Acesso à fonteDOIComo citar
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    • ABNT

      VERDONCK, Patrick Bernard e BRASSEUR, G. e COOPMANS, F. Laser enhanced polymer etching in different ambients. Microelectronic Engineering, v. 9, p. 507-510, 1989Tradução . . Disponível em: https://doi.org/10.1016/0167-9317(89)90111-1. Acesso em: 16 nov. 2025.
    • APA

      Verdonck, P. B., Brasseur, G., & Coopmans, F. (1989). Laser enhanced polymer etching in different ambients. Microelectronic Engineering, 9, 507-510. doi:10.1016/0167-9317(89)90111-1
    • NLM

      Verdonck PB, Brasseur G, Coopmans F. Laser enhanced polymer etching in different ambients [Internet]. Microelectronic Engineering. 1989 ; 9 507-510.[citado 2025 nov. 16 ] Available from: https://doi.org/10.1016/0167-9317(89)90111-1
    • Vancouver

      Verdonck PB, Brasseur G, Coopmans F. Laser enhanced polymer etching in different ambients [Internet]. Microelectronic Engineering. 1989 ; 9 507-510.[citado 2025 nov. 16 ] Available from: https://doi.org/10.1016/0167-9317(89)90111-1

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