ReP USP - Resultado da busca

Trabalho de evento
Behavior of the graded-channel fully-depleted SOI nMOSFET in suthreshold regime (2001)
Gimenez, Salvador Pinillos ; Pavanello, Marcelo Antonio ; Martino, João Antonio
Source: SBMicro 2001: proceedings. Conference titles: International Conference on Microelectronics and Packaging. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
GIMENEZ, Salvador Pinillos e PAVANELLO, Marcelo Antonio e MARTINO, João Antonio. Behavior of the graded-channel fully-depleted SOI nMOSFET in suthreshold regime. 2001, Anais.. Brasília: SBMicro, 2001. . Acesso em: 16 nov. 2025.
APA
Gimenez, S. P., Pavanello, M. A., & Martino, J. A. (2001). Behavior of the graded-channel fully-depleted SOI nMOSFET in suthreshold regime. In SBMicro 2001: proceedings. Brasília: SBMicro.
NLM
Gimenez SP, Pavanello MA, Martino JA. Behavior of the graded-channel fully-depleted SOI nMOSFET in suthreshold regime. SBMicro 2001: proceedings. 2001 ;[citado 2025 nov. 16 ]
Vancouver
Gimenez SP, Pavanello MA, Martino JA. Behavior of the graded-channel fully-depleted SOI nMOSFET in suthreshold regime. SBMicro 2001: proceedings. 2001 ;[citado 2025 nov. 16 ]
Trabalho de evento
Improved current mirror output performance by using graded-channel SOI nMOSFETs (2001)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: SBMicro 2001: proceedings. Conference titles: International Conference on Microelectronics and Packaging. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Improved current mirror output performance by using graded-channel SOI nMOSFETs. 2001, Anais.. Brasília: SBMicro, 2001. . Acesso em: 16 nov. 2025.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2001). Improved current mirror output performance by using graded-channel SOI nMOSFETs. In SBMicro 2001: proceedings. Brasília: SBMicro.
NLM
Pavanello MA, Martino JA, Flandre D. Improved current mirror output performance by using graded-channel SOI nMOSFETs. SBMicro 2001: proceedings. 2001 ;[citado 2025 nov. 16 ]
Vancouver
Pavanello MA, Martino JA, Flandre D. Improved current mirror output performance by using graded-channel SOI nMOSFETs. SBMicro 2001: proceedings. 2001 ;[citado 2025 nov. 16 ]
Trabalho de evento
Comparison of analog performance in conventional and graded-channel fully-depleted SOI MOSFETs (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: SBMicro 2000: proceedings. Conference titles: International Conference on Microelectronics and Packaging. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Comparison of analog performance in conventional and graded-channel fully-depleted SOI MOSFETs. 2000, Anais.. Manaus: SBMicro/UA/UFRGS/UNICAMP/USP, 2000. . Acesso em: 16 nov. 2025.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2000). Comparison of analog performance in conventional and graded-channel fully-depleted SOI MOSFETs. In SBMicro 2000: proceedings. Manaus: SBMicro/UA/UFRGS/UNICAMP/USP.
NLM
Pavanello MA, Martino JA, Flandre D. Comparison of analog performance in conventional and graded-channel fully-depleted SOI MOSFETs. SBMicro 2000: proceedings. 2000 ;[citado 2025 nov. 16 ]
Vancouver
Pavanello MA, Martino JA, Flandre D. Comparison of analog performance in conventional and graded-channel fully-depleted SOI MOSFETs. SBMicro 2000: proceedings. 2000 ;[citado 2025 nov. 16 ]
Trabalho de evento
Parasitic bipolar effects in graded-channel fully-depleted silicon-on-insulator nMOSFET (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: SBMicro 2000: proceedings. Conference titles: International Conference on Microelectronics and Packaging. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Parasitic bipolar effects in graded-channel fully-depleted silicon-on-insulator nMOSFET. 2000, Anais.. Manaus: SBMicro/UA/UFRGS/UNICAMP/USP, 2000. . Acesso em: 16 nov. 2025.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2000). Parasitic bipolar effects in graded-channel fully-depleted silicon-on-insulator nMOSFET. In SBMicro 2000: proceedings. Manaus: SBMicro/UA/UFRGS/UNICAMP/USP.
NLM
Pavanello MA, Martino JA, Flandre D. Parasitic bipolar effects in graded-channel fully-depleted silicon-on-insulator nMOSFET. SBMicro 2000: proceedings. 2000 ;[citado 2025 nov. 16 ]
Vancouver
Pavanello MA, Martino JA, Flandre D. Parasitic bipolar effects in graded-channel fully-depleted silicon-on-insulator nMOSFET. SBMicro 2000: proceedings. 2000 ;[citado 2025 nov. 16 ]
Trabalho de evento
Extraction of the interface charge density at the silicon substrate interface in SOI MOSFET's at cryogenic temperatures (1999)
Pavanello, Marcelo Antonio ; Martino, João Antonio
Source: ICMP 99 : Technical Digest. Conference titles: International Conference on Microelectronics and Packaging. Unidade: EP
Assunto: SEMICONDUTORES
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio. Extraction of the interface charge density at the silicon substrate interface in SOI MOSFET's at cryogenic temperatures. 1999, Anais.. São Paulo: SBMicro/IMAPS, 1999. . Acesso em: 16 nov. 2025.
APA
Pavanello, M. A., & Martino, J. A. (1999). Extraction of the interface charge density at the silicon substrate interface in SOI MOSFET's at cryogenic temperatures. In ICMP 99 : Technical Digest. São Paulo: SBMicro/IMAPS.
NLM
Pavanello MA, Martino JA. Extraction of the interface charge density at the silicon substrate interface in SOI MOSFET's at cryogenic temperatures. ICMP 99 : Technical Digest. 1999 ;[citado 2025 nov. 16 ]
Vancouver
Pavanello MA, Martino JA. Extraction of the interface charge density at the silicon substrate interface in SOI MOSFET's at cryogenic temperatures. ICMP 99 : Technical Digest. 1999 ;[citado 2025 nov. 16 ]
Trabalho de evento
The graded-channel SOI NMOSFET and its potential to analog applications (1999)
Pavanello, Marcelo Antonio ; Dessard, Vincent; Flandre, Denis ; Martino, João Antonio
Source: ICMP 99 : Technical Digest. Conference titles: International Conference on Microelectronics and Packaging. Unidade: EP
Assunto: ENGENHARIA ELÉTRICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. The graded-channel SOI NMOSFET and its potential to analog applications. 1999, Anais.. São Paulo: SBMicro/IMAPS, 1999. . Acesso em: 16 nov. 2025.
APA
Pavanello, M. A., Dessard, V., Flandre, D., & Martino, J. A. (1999). The graded-channel SOI NMOSFET and its potential to analog applications. In ICMP 99 : Technical Digest. São Paulo: SBMicro/IMAPS.
NLM
Pavanello MA, Dessard V, Flandre D, Martino JA. The graded-channel SOI NMOSFET and its potential to analog applications. ICMP 99 : Technical Digest. 1999 ;[citado 2025 nov. 16 ]
Vancouver
Pavanello MA, Dessard V, Flandre D, Martino JA. The graded-channel SOI NMOSFET and its potential to analog applications. ICMP 99 : Technical Digest. 1999 ;[citado 2025 nov. 16 ]
Trabalho de evento
Effect of the substrate potential drop in accumulation-mode SOI pMOSFETs subthreshold slope (1998)
Pavanello, Marcelo Antonio ; Martino, João Antonio
Source: SBMicro'ICMP 98 : Proceedings. Conference titles: International Conference on Microelectronics and Packaging. Unidade: EP
Assunto: SEMICONDUTORES
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio. Effect of the substrate potential drop in accumulation-mode SOI pMOSFETs subthreshold slope. 1998, Anais.. Curitiba: SBMicro/LACTRO/LAC, 1998. . Acesso em: 16 nov. 2025.
APA
Pavanello, M. A., & Martino, J. A. (1998). Effect of the substrate potential drop in accumulation-mode SOI pMOSFETs subthreshold slope. In SBMicro'ICMP 98 : Proceedings. Curitiba: SBMicro/LACTRO/LAC.
NLM
Pavanello MA, Martino JA. Effect of the substrate potential drop in accumulation-mode SOI pMOSFETs subthreshold slope. SBMicro'ICMP 98 : Proceedings. 1998 ;[citado 2025 nov. 16 ]
Vancouver
Pavanello MA, Martino JA. Effect of the substrate potential drop in accumulation-mode SOI pMOSFETs subthreshold slope. SBMicro'ICMP 98 : Proceedings. 1998 ;[citado 2025 nov. 16 ]

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