ReP USP - Resultado da busca

Trabalho de evento
Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements (2012)
Mariniello, Genaro ; Doria, Rodrigo Trevisoli ; Trevisoli, Renan ; Souza, Michelly de ; Pavanello, Marcelo Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MARINIELLO, Genaro et al. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0231ecst. Acesso em: 11 nov. 2024.
APA
Mariniello, G., Doria, R. T., Trevisoli, R., Souza, M. de, & Pavanello, M. A. (2012). Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0231ecst
NLM
Mariniello G, Doria RT, Trevisoli R, Souza M de, Pavanello MA. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 11 ] Available from: https://doi.org/10.1149/04901.0231ecst
Vancouver
Mariniello G, Doria RT, Trevisoli R, Souza M de, Pavanello MA. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 11 ] Available from: https://doi.org/10.1149/04901.0231ecst
Trabalho de evento
Comparative study of biaxial and uniaxial mechanical stress influence on the low frequency noise of fully depleted SOI nMOSFETs operating in triode and saturation regime (2012)
Souza, Marcio Alves Sodré de; Doria, Rodrigo Trevisoli ; Souza, Michelly de ; Martino, João Antonio ; Pavanello, Marcelo Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SOUZA, Marcio Alves Sodré de et al. Comparative study of biaxial and uniaxial mechanical stress influence on the low frequency noise of fully depleted SOI nMOSFETs operating in triode and saturation regime. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0077ecst. Acesso em: 11 nov. 2024.
APA
Souza, M. A. S. de, Doria, R. T., Souza, M. de, Martino, J. A., & Pavanello, M. A. (2012). Comparative study of biaxial and uniaxial mechanical stress influence on the low frequency noise of fully depleted SOI nMOSFETs operating in triode and saturation regime. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0077ecst
NLM
Souza MAS de, Doria RT, Souza M de, Martino JA, Pavanello MA. Comparative study of biaxial and uniaxial mechanical stress influence on the low frequency noise of fully depleted SOI nMOSFETs operating in triode and saturation regime [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 11 ] Available from: https://doi.org/10.1149/04901.0077ecst
Vancouver
Souza MAS de, Doria RT, Souza M de, Martino JA, Pavanello MA. Comparative study of biaxial and uniaxial mechanical stress influence on the low frequency noise of fully depleted SOI nMOSFETs operating in triode and saturation regime [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 11 ] Available from: https://doi.org/10.1149/04901.0077ecst
Trabalho de evento
Liquid helium temperature operation of graded-channel SOI nMOSFETs (2012)
Souza, Michelly de ; Kilchytska, Valeriya ; Flandre, Denis ; Pavanello, Marcelo Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SOUZA, Michelly de et al. Liquid helium temperature operation of graded-channel SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0135ecst. Acesso em: 11 nov. 2024.
APA
Souza, M. de, Kilchytska, V., Flandre, D., & Pavanello, M. A. (2012). Liquid helium temperature operation of graded-channel SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0135ecst
NLM
Souza M de, Kilchytska V, Flandre D, Pavanello MA. Liquid helium temperature operation of graded-channel SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 11 ] Available from: https://doi.org/10.1149/04901.0135ecst
Vancouver
Souza M de, Kilchytska V, Flandre D, Pavanello MA. Liquid helium temperature operation of graded-channel SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 11 ] Available from: https://doi.org/10.1149/04901.0135ecst
Trabalho de evento
Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors (2012)
Trevisoli, Renan ; Doria, Rodrigo Trevisoli ; Souza, Michelly de ; Pavanello, Marcelo Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
TREVISOLI, Renan et al. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0207ecst. Acesso em: 11 nov. 2024.
APA
Trevisoli, R., Doria, R. T., Souza, M. de, & Pavanello, M. A. (2012). Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0207ecst
NLM
Trevisoli R, Doria RT, Souza M de, Pavanello MA. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 11 ] Available from: https://doi.org/10.1149/04901.0207ecst
Vancouver
Trevisoli R, Doria RT, Souza M de, Pavanello MA. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 11 ] Available from: https://doi.org/10.1149/04901.0207ecst
Trabalho de evento
Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance (2012)
Doria, Rodrigo Trevisoli ; Trevisoli, Renan ; Souza, Michelly de ; Pavanello, Marcelo Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
DORIA, Rodrigo Trevisoli et al. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0215ecst. Acesso em: 11 nov. 2024.
APA
Doria, R. T., Trevisoli, R., Souza, M. de, & Pavanello, M. A. (2012). Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0215ecst
NLM
Doria RT, Trevisoli R, Souza M de, Pavanello MA. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 11 ] Available from: https://doi.org/10.1149/04901.0215ecst
Vancouver
Doria RT, Trevisoli R, Souza M de, Pavanello MA. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 11 ] Available from: https://doi.org/10.1149/04901.0215ecst

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