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Trabalho de evento
A PD-based methodology to enhance efficiency in testbenches with random stimulation (2009)
Castro Márquez, Carlos Iván; Strum, Marius; Wang, Jiang Chau
Source: SBCCI 2009: Proceedings. Conference titles: Symposium on Integrated Circuits and Systems Design. Unidade: EP
Assunto: ALGORITMOS
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ABNT
CASTRO MÁRQUEZ, Carlos Iván e STRUM, Marius e WANG, Jiang Chau. A PD-based methodology to enhance efficiency in testbenches with random stimulation. 2009, Anais.. Natal: Sociedade Brasileira de Computação, 2009. Disponível em: https://doi.org/10.1145/1601896.1601921. Acesso em: 09 jul. 2025.
APA
Castro Márquez, C. I., Strum, M., & Wang, J. C. (2009). A PD-based methodology to enhance efficiency in testbenches with random stimulation. In SBCCI 2009: Proceedings. Natal: Sociedade Brasileira de Computação. doi:10.1145/1601896.1601921
NLM
Castro Márquez CI, Strum M, Wang JC. A PD-based methodology to enhance efficiency in testbenches with random stimulation [Internet]. SBCCI 2009: Proceedings. 2009 ;[citado 2025 jul. 09 ] Available from: https://doi.org/10.1145/1601896.1601921
Vancouver
Castro Márquez CI, Strum M, Wang JC. A PD-based methodology to enhance efficiency in testbenches with random stimulation [Internet]. SBCCI 2009: Proceedings. 2009 ;[citado 2025 jul. 09 ] Available from: https://doi.org/10.1145/1601896.1601921
Trabalho de evento
A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer (2005)
Gómez Argüello, Angel María; Soares Junior, João Navarro ; Van Noije, Wilhelmus Adrianus Maria
Source: SBCCI 2005. Conference titles: Symposium on Integrated Circuits and Systems Design. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
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ABNT
GÓMEZ ARGÜELLO, Angel María e SOARES JUNIOR, João Navarro e VAN NOIJE, Wilhelmus Adrianus Maria. A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer. 2005, Anais.. New York: ACM, 2005. . Acesso em: 09 jul. 2025.
APA
Gómez Argüello, A. M., Soares Junior, J. N., & Van Noije, W. A. M. (2005). A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer. In SBCCI 2005. New York: ACM.
NLM
Gómez Argüello AM, Soares Junior JN, Van Noije WAM. A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer. SBCCI 2005. 2005 ;[citado 2025 jul. 09 ]
Vancouver
Gómez Argüello AM, Soares Junior JN, Van Noije WAM. A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer. SBCCI 2005. 2005 ;[citado 2025 jul. 09 ]
Trabalho de evento
Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers (2005)
Oliveira, Duarte Lopes de; Strum, Marius; Wang, Jiang Chau
Source: SBCCI 2005. Conference titles: Symposium on Integrated Circuits and Systems Design. Unidade: EP
Subjects: CONTROLADORES PROGRAMÁVEIS, SISTEMAS DE CONTROLE
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ABNT
OLIVEIRA, Duarte Lopes de e STRUM, Marius e WANG, Jiang Chau. Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. 2005, Anais.. New York: ACM, 2005. . Acesso em: 09 jul. 2025.
APA
Oliveira, D. L. de, Strum, M., & Wang, J. C. (2005). Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. In SBCCI 2005. New York: ACM.
NLM
Oliveira DL de, Strum M, Wang JC. Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. SBCCI 2005. 2005 ;[citado 2025 jul. 09 ]
Vancouver
Oliveira DL de, Strum M, Wang JC. Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. SBCCI 2005. 2005 ;[citado 2025 jul. 09 ]
Trabalho de evento
Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs (2003)
Gimenez, Salvador Pinillos ; Pavanello, Marcelo Antonio ; Martino, João Antonio ; Adriaensen, S.; Flandre, Denis
Source: SBCCI 03 : proceedings. Conference titles: Symposium on Integrated Circuits and Systems Design. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
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ABNT
GIMENEZ, Salvador Pinillos et al. Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs. 2003, Anais.. Piscataway: IEEE Computer Society, 2003. . Acesso em: 09 jul. 2025.
APA
Gimenez, S. P., Pavanello, M. A., Martino, J. A., Adriaensen, S., & Flandre, D. (2003). Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs. In SBCCI 03 : proceedings. Piscataway: IEEE Computer Society.
NLM
Gimenez SP, Pavanello MA, Martino JA, Adriaensen S, Flandre D. Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs. SBCCI 03 : proceedings. 2003 ;[citado 2025 jul. 09 ]
Vancouver
Gimenez SP, Pavanello MA, Martino JA, Adriaensen S, Flandre D. Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs. SBCCI 03 : proceedings. 2003 ;[citado 2025 jul. 09 ]
Trabalho de evento
Analog circuit design using graded-channel SOI NMOSFETs (2001)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: Proceedings. Conference titles: Symposium on Integrated Circuits and Systems Design. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Analog circuit design using graded-channel SOI NMOSFETs. 2001, Anais.. Piscataway: IEEE, 2001. . Acesso em: 09 jul. 2025.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2001). Analog circuit design using graded-channel SOI NMOSFETs. In Proceedings. Piscataway: IEEE.
NLM
Pavanello MA, Martino JA, Flandre D. Analog circuit design using graded-channel SOI NMOSFETs. Proceedings. 2001 ;[citado 2025 jul. 09 ]
Vancouver
Pavanello MA, Martino JA, Flandre D. Analog circuit design using graded-channel SOI NMOSFETs. Proceedings. 2001 ;[citado 2025 jul. 09 ]
Trabalho de evento
Revisiting hamiltoniam decomposition of the hypercube (2000)
Okuda, Kunio; Song, Siang Wun
Source: Proceedings. Conference titles: Symposium on Integrated Circuits and Systems Design. Unidade: IME
Assunto: ARQUITETURA E ORGANIZAÇÃO DE COMPUTADORES
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
OKUDA, Kunio e SONG, Siang Wun. Revisiting hamiltoniam decomposition of the hypercube. 2000, Anais.. Los Alamitos: IEEE, 2000. Disponível em: https://doi.org/10.1109/SBCCI.2000.876008. Acesso em: 09 jul. 2025.
APA
Okuda, K., & Song, S. W. (2000). Revisiting hamiltoniam decomposition of the hypercube. In Proceedings. Los Alamitos: IEEE. doi:10.1109/SBCCI.2000.876008
NLM
Okuda K, Song SW. Revisiting hamiltoniam decomposition of the hypercube [Internet]. Proceedings. 2000 ;[citado 2025 jul. 09 ] Available from: https://doi.org/10.1109/SBCCI.2000.876008
Vancouver
Okuda K, Song SW. Revisiting hamiltoniam decomposition of the hypercube [Internet]. Proceedings. 2000 ;[citado 2025 jul. 09 ] Available from: https://doi.org/10.1109/SBCCI.2000.876008
Trabalho de evento
Synthesis of the high performance extended burst mode asynchronous state machines (2000)
Oliveira, Duarte Lopes de; Strum, Marius; Wang, Jiang Chau ; Cunha, Wagner Chiepa
Source: Proceedings. Conference titles: Symposium on Integrated Circuits and Systems Design. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
OLIVEIRA, Duarte Lopes de et al. Synthesis of the high performance extended burst mode asynchronous state machines. 2000, Anais.. Los Alamitos: IEEE, 2000. . Acesso em: 09 jul. 2025.
APA
Oliveira, D. L. de, Strum, M., Wang, J. C., & Cunha, W. C. (2000). Synthesis of the high performance extended burst mode asynchronous state machines. In Proceedings. Los Alamitos: IEEE.
NLM
Oliveira DL de, Strum M, Wang JC, Cunha WC. Synthesis of the high performance extended burst mode asynchronous state machines. Proceedings. 2000 ;[citado 2025 jul. 09 ]
Vancouver
Oliveira DL de, Strum M, Wang JC, Cunha WC. Synthesis of the high performance extended burst mode asynchronous state machines. Proceedings. 2000 ;[citado 2025 jul. 09 ]
Trabalho de evento
On the choice of models of computation for writing executable specifications of system level designs (2000)
Jeukens, Ivan; Strum, Marius
Source: Proceedings. Conference titles: Symposium on Integrated Circuits and Systems Design. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
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ABNT
JEUKENS, Ivan e STRUM, Marius. On the choice of models of computation for writing executable specifications of system level designs. 2000, Anais.. Los Alamitos: IEEE, 2000. . Acesso em: 09 jul. 2025.
APA
Jeukens, I., & Strum, M. (2000). On the choice of models of computation for writing executable specifications of system level designs. In Proceedings. Los Alamitos: IEEE.
NLM
Jeukens I, Strum M. On the choice of models of computation for writing executable specifications of system level designs. Proceedings. 2000 ;[citado 2025 jul. 09 ]
Vancouver
Jeukens I, Strum M. On the choice of models of computation for writing executable specifications of system level designs. Proceedings. 2000 ;[citado 2025 jul. 09 ]
Trabalho de evento
Prototyping a pager-like device using FPGAs: design of an object finder (2000)
Cerezo Vásquez, Gustavo Adolfo; Van Noije, Wilhelmus Adrianus Maria ; Barbin, Silvio Ernesto
Source: Proceedings. Conference titles: Symposium on Integrated Circuits and Systems Design. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
CEREZO VÁSQUEZ, Gustavo Adolfo e VAN NOIJE, Wilhelmus Adrianus Maria e BARBIN, Silvio Ernesto. Prototyping a pager-like device using FPGAs: design of an object finder. 2000, Anais.. Los Alamitos: IEEE, 2000. Disponível em: https://doi.org/10.1109/SBCCI.2000.876029. Acesso em: 09 jul. 2025.
APA
Cerezo Vásquez, G. A., Van Noije, W. A. M., & Barbin, S. E. (2000). Prototyping a pager-like device using FPGAs: design of an object finder. In Proceedings. Los Alamitos: IEEE. doi:10.1109/SBCCI.2000.876029
NLM
Cerezo Vásquez GA, Van Noije WAM, Barbin SE. Prototyping a pager-like device using FPGAs: design of an object finder [Internet]. Proceedings. 2000 ;[citado 2025 jul. 09 ] Available from: https://doi.org/10.1109/SBCCI.2000.876029
Vancouver
Cerezo Vásquez GA, Van Noije WAM, Barbin SE. Prototyping a pager-like device using FPGAs: design of an object finder [Internet]. Proceedings. 2000 ;[citado 2025 jul. 09 ] Available from: https://doi.org/10.1109/SBCCI.2000.876029
Trabalho de evento
A data path synthesis method to self-testable application specific integrated circuit (ASIC) (2000)
Costa, Jefferson Perez R.; Vale Neto, José Vieira do
Source: Proceedings. Conference titles: Symposium on Integrated Circuits and Systems Design. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
COSTA, Jefferson Perez R. e VALE NETO, José Vieira do. A data path synthesis method to self-testable application specific integrated circuit (ASIC). 2000, Anais.. Los Alamitos: IEEE, 2000. . Acesso em: 09 jul. 2025.
APA
Costa, J. P. R., & Vale Neto, J. V. do. (2000). A data path synthesis method to self-testable application specific integrated circuit (ASIC). In Proceedings. Los Alamitos: IEEE.
NLM
Costa JPR, Vale Neto JV do. A data path synthesis method to self-testable application specific integrated circuit (ASIC). Proceedings. 2000 ;[citado 2025 jul. 09 ]
Vancouver
Costa JPR, Vale Neto JV do. A data path synthesis method to self-testable application specific integrated circuit (ASIC). Proceedings. 2000 ;[citado 2025 jul. 09 ]
Trabalho de evento
Modeling and E1/TU12 mapper for SDH systems (2000)
Silveira, Reinaldo; Van Noije, Wilhelmus Adrianus Maria
Source: Proceedings. Conference titles: Symposium on Integrated Circuits and Systems Design. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SILVEIRA, Reinaldo e VAN NOIJE, Wilhelmus Adrianus Maria. Modeling and E1/TU12 mapper for SDH systems. 2000, Anais.. Los Alamitos: IEEE, 2000. . Acesso em: 09 jul. 2025.
APA
Silveira, R., & Van Noije, W. A. M. (2000). Modeling and E1/TU12 mapper for SDH systems. In Proceedings. Los Alamitos: IEEE.
NLM
Silveira R, Van Noije WAM. Modeling and E1/TU12 mapper for SDH systems. Proceedings. 2000 ;[citado 2025 jul. 09 ]
Vancouver
Silveira R, Van Noije WAM. Modeling and E1/TU12 mapper for SDH systems. Proceedings. 2000 ;[citado 2025 jul. 09 ]
Trabalho de evento
The use of extended TSPC CMOS structures to build circuits with doubled input/output data throughput (2000)
Soares Junior, João Navarro ; Van Noije, Wilhelmus Adrianus Maria
Source: Proceedings. Conference titles: Symposium on Integrated Circuits and Systems Design. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SOARES JUNIOR, João Navarro e VAN NOIJE, Wilhelmus Adrianus Maria. The use of extended TSPC CMOS structures to build circuits with doubled input/output data throughput. 2000, Anais.. Los Alamitos: IEEE, 2000. . Acesso em: 09 jul. 2025.
APA
Soares Junior, J. N., & Van Noije, W. A. M. (2000). The use of extended TSPC CMOS structures to build circuits with doubled input/output data throughput. In Proceedings. Los Alamitos: IEEE.
NLM
Soares Junior JN, Van Noije WAM. The use of extended TSPC CMOS structures to build circuits with doubled input/output data throughput. Proceedings. 2000 ;[citado 2025 jul. 09 ]
Vancouver
Soares Junior JN, Van Noije WAM. The use of extended TSPC CMOS structures to build circuits with doubled input/output data throughput. Proceedings. 2000 ;[citado 2025 jul. 09 ]

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