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Artigo de periodico
Application-oriented cache memory configuration for energy efficiency in multi-cores (2015)
Silva, Bruno de Abreu; Cuminato, Lucas A; Delbem, Alexandre Cláudio Botazzo ; Diniz, Pedro C; Bonato, Vanderlei
Source: IET Computers and Digital Techniques. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SILVA, Bruno de Abreu et al. Application-oriented cache memory configuration for energy efficiency in multi-cores. IET Computers and Digital Techniques, v. Fe 2015, n. 1, p. 73-81, 2015Tradução . . Disponível em: https://doi.org/10.1049/iet-cdt.2014.0091. Acesso em: 10 nov. 2024.
APA
Silva, B. de A., Cuminato, L. A., Delbem, A. C. B., Diniz, P. C., & Bonato, V. (2015). Application-oriented cache memory configuration for energy efficiency in multi-cores. IET Computers and Digital Techniques, Fe 2015( 1), 73-81. doi:10.1049/iet-cdt.2014.0091
NLM
Silva B de A, Cuminato LA, Delbem ACB, Diniz PC, Bonato V. Application-oriented cache memory configuration for energy efficiency in multi-cores [Internet]. IET Computers and Digital Techniques. 2015 ; Fe 2015( 1): 73-81.[citado 2024 nov. 10 ] Available from: https://doi.org/10.1049/iet-cdt.2014.0091
Vancouver
Silva B de A, Cuminato LA, Delbem ACB, Diniz PC, Bonato V. Application-oriented cache memory configuration for energy efficiency in multi-cores [Internet]. IET Computers and Digital Techniques. 2015 ; Fe 2015( 1): 73-81.[citado 2024 nov. 10 ] Available from: https://doi.org/10.1049/iet-cdt.2014.0091
Trabalho de evento-resumo
Parameterizable ethernet network-on-chip architecture on FPGA (2015)
Cunha Junior, Helio Fernandes da; Silva, Bruno de Abreu; Bonato, Vanderlei
Source: Proceedings. Conference titles: Euromicro Conference on Digital System Design - DSD. Unidade: ICMC
Subjects: COMPUTAÇÃO RECONFIGURÁVEL, SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
CUNHA JUNIOR, Helio Fernandes da e SILVA, Bruno de Abreu e BONATO, Vanderlei. Parameterizable ethernet network-on-chip architecture on FPGA. 2015, Anais.. Los Alamitos, CA: IEEE, 2015. Disponível em: https://doi.org/10.1109/DSD.2015.101. Acesso em: 10 nov. 2024.
APA
Cunha Junior, H. F. da, Silva, B. de A., & Bonato, V. (2015). Parameterizable ethernet network-on-chip architecture on FPGA. In Proceedings. Los Alamitos, CA: IEEE. doi:10.1109/DSD.2015.101
NLM
Cunha Junior HF da, Silva B de A, Bonato V. Parameterizable ethernet network-on-chip architecture on FPGA [Internet]. Proceedings. 2015 ;[citado 2024 nov. 10 ] Available from: https://doi.org/10.1109/DSD.2015.101
Vancouver
Cunha Junior HF da, Silva B de A, Bonato V. Parameterizable ethernet network-on-chip architecture on FPGA [Internet]. Proceedings. 2015 ;[citado 2024 nov. 10 ] Available from: https://doi.org/10.1109/DSD.2015.101
Artigo de periodico
Tag management in a reconfigurable tagged-token dataflow architecture (2015)
Silva, Bruno de Abreu; Silva, Jorge Luiz e
Source: WSEAS Transactions on Computers. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SILVA, Bruno de Abreu e SILVA, Jorge Luiz e. Tag management in a reconfigurable tagged-token dataflow architecture. WSEAS Transactions on Computers, v. 14, p. 730-739, 2015Tradução . . Disponível em: http://www.wseas.org/multimedia/journals/computers/2015/b425705-187.pdf. Acesso em: 10 nov. 2024.
APA
Silva, B. de A., & Silva, J. L. e. (2015). Tag management in a reconfigurable tagged-token dataflow architecture. WSEAS Transactions on Computers, 14, 730-739. Recuperado de http://www.wseas.org/multimedia/journals/computers/2015/b425705-187.pdf
NLM
Silva B de A, Silva JL e. Tag management in a reconfigurable tagged-token dataflow architecture [Internet]. WSEAS Transactions on Computers. 2015 ; 14 730-739.[citado 2024 nov. 10 ] Available from: http://www.wseas.org/multimedia/journals/computers/2015/b425705-187.pdf
Vancouver
Silva B de A, Silva JL e. Tag management in a reconfigurable tagged-token dataflow architecture [Internet]. WSEAS Transactions on Computers. 2015 ; 14 730-739.[citado 2024 nov. 10 ] Available from: http://www.wseas.org/multimedia/journals/computers/2015/b425705-187.pdf
Trabalho de evento-resumo
Power/performance optimization in FPGA-based asymmetric multi-core systems (2012)
Silva, Bruno de Abreu; Bonato, Vanderlei
Source: Proceedings. Conference titles: International Conference on Field Programmable Logic and Applications - FPL 2012. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SILVA, Bruno de Abreu e BONATO, Vanderlei. Power/performance optimization in FPGA-based asymmetric multi-core systems. 2012, Anais.. New York: IEEE, 2012. Disponível em: https://doi.org/10.1109/FPL.2012.6339197. Acesso em: 10 nov. 2024.
APA
Silva, B. de A., & Bonato, V. (2012). Power/performance optimization in FPGA-based asymmetric multi-core systems. In Proceedings. New York: IEEE. doi:10.1109/FPL.2012.6339197
NLM
Silva B de A, Bonato V. Power/performance optimization in FPGA-based asymmetric multi-core systems [Internet]. Proceedings. 2012 ;[citado 2024 nov. 10 ] Available from: https://doi.org/10.1109/FPL.2012.6339197
Vancouver
Silva B de A, Bonato V. Power/performance optimization in FPGA-based asymmetric multi-core systems [Internet]. Proceedings. 2012 ;[citado 2024 nov. 10 ] Available from: https://doi.org/10.1109/FPL.2012.6339197
Trabalho de evento
Reducing the overall cache miss rate using different cache sizes for heterogeneous multi-core processors (2012)
Silva, Bruno de Abreu; Cuminato, Lucas Albers; Bonato, Vanderlei
Source: Proceedings. Conference titles: International Conference on Reconfigurable Computing and FPGAs - ReConFig 2012. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SILVA, Bruno de Abreu e CUMINATO, Lucas Albers e BONATO, Vanderlei. Reducing the overall cache miss rate using different cache sizes for heterogeneous multi-core processors. 2012, Anais.. New York: IEEE, 2012. . Acesso em: 10 nov. 2024.
APA
Silva, B. de A., Cuminato, L. A., & Bonato, V. (2012). Reducing the overall cache miss rate using different cache sizes for heterogeneous multi-core processors. In Proceedings. New York: IEEE.
NLM
Silva B de A, Cuminato LA, Bonato V. Reducing the overall cache miss rate using different cache sizes for heterogeneous multi-core processors. Proceedings. 2012 ;[citado 2024 nov. 10 ]
Vancouver
Silva B de A, Cuminato LA, Bonato V. Reducing the overall cache miss rate using different cache sizes for heterogeneous multi-core processors. Proceedings. 2012 ;[citado 2024 nov. 10 ]

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