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Artigo de periodico
Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs (2000)
Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
NICOLETT, Aparecido Sirley et al. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs. Solid-State Electronics, v. No 2000, n. 11, p. 1961-1969, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00166-0. Acesso em: 09 out. 2024.
APA
Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2000). Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs. Solid-State Electronics, No 2000( 11), 1961-1969. doi:10.1016/s0038-1101(00)00166-0
NLM
Nicolett AS, Martino JA, Simoen E, Claeys C. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs [Internet]. Solid-State Electronics. 2000 ; No 2000( 11): 1961-1969.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0038-1101(00)00166-0
Vancouver
Nicolett AS, Martino JA, Simoen E, Claeys C. Simultaneous extraction of the silicon film and front oxide thicknesses on fully depleted SOI nMOSFETs [Internet]. Solid-State Electronics. 2000 ; No 2000( 11): 1961-1969.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0038-1101(00)00166-0
Artigo de periodico
Analog performance and application of graded-channel fully depleted SOI MOSFETs (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Dessard, Vincent; Flandre, Denis
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Analog performance and application of graded-channel fully depleted SOI MOSFETs. Solid-State Electronics, v. 44, n. 7, p. 1219-1222, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00034-4. Acesso em: 09 out. 2024.
APA
Pavanello, M. A., Martino, J. A., Dessard, V., & Flandre, D. (2000). Analog performance and application of graded-channel fully depleted SOI MOSFETs. Solid-State Electronics, 44( 7), 1219-1222. doi:10.1016/s0038-1101(00)00034-4
NLM
Pavanello MA, Martino JA, Dessard V, Flandre D. Analog performance and application of graded-channel fully depleted SOI MOSFETs [Internet]. Solid-State Electronics. 2000 ; 44( 7): 1219-1222.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0038-1101(00)00034-4
Vancouver
Pavanello MA, Martino JA, Dessard V, Flandre D. Analog performance and application of graded-channel fully depleted SOI MOSFETs [Internet]. Solid-State Electronics. 2000 ; 44( 7): 1219-1222.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0038-1101(00)00034-4
Artigo de periodico
Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, v. 44, n. 6, p. 917-922, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00032-0. Acesso em: 09 out. 2024.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2000). Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects. Solid-State Electronics, 44( 6), 917-922. doi:10.1016/s0038-1101(00)00032-0
NLM
Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0
Vancouver
Pavanello MA, Martino JA, Flandre D. Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects [Internet]. Solid-State Electronics. 2000 ; 44( 6): 917-922.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0038-1101(00)00032-0
Artigo de periodico
Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect (2000)
Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
NICOLETT, Aparecido Sirley et al. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect. Solid-State Electronics, v. 44, n. 4, p. 677-684, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(99)00293-2. Acesso em: 09 out. 2024.
APA
Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (2000). Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect. Solid-State Electronics, 44( 4), 677-684. doi:10.1016/s0038-1101(99)00293-2
NLM
Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect [Internet]. Solid-State Electronics. 2000 ; 44( 4): 677-684.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0038-1101(99)00293-2
Vancouver
Nicolett AS, Martino JA, Simoen E, Claeys C. Extraction of the lightly doped drain concentration of fully depleted SOI nMOSFETs using the back gate bias effect [Internet]. Solid-State Electronics. 2000 ; 44( 4): 677-684.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0038-1101(99)00293-2
Artigo de periodico
Mechanisms of surface roughness induced in silicon by fluorine containing plasmas (1997)
Mansano, Ronaldo Domingues ; Verdonck, Patrick Bernard; Maciel, Homero Santiago
Source: Vaccum. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MANSANO, Ronaldo Domingues e VERDONCK, Patrick Bernard e MACIEL, Homero Santiago. Mechanisms of surface roughness induced in silicon by fluorine containing plasmas. Vaccum, v. 48, n. 7-9, p. 677-679, 1997Tradução . . Disponível em: https://doi.org/10.1016/s0042-207x(97)00067-5. Acesso em: 09 out. 2024.
APA
Mansano, R. D., Verdonck, P. B., & Maciel, H. S. (1997). Mechanisms of surface roughness induced in silicon by fluorine containing plasmas. Vaccum, 48( 7-9), 677-679. doi:10.1016/s0042-207x(97)00067-5
NLM
Mansano RD, Verdonck PB, Maciel HS. Mechanisms of surface roughness induced in silicon by fluorine containing plasmas [Internet]. Vaccum. 1997 ; 48( 7-9): 677-679.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0042-207x(97)00067-5
Vancouver
Mansano RD, Verdonck PB, Maciel HS. Mechanisms of surface roughness induced in silicon by fluorine containing plasmas [Internet]. Vaccum. 1997 ; 48( 7-9): 677-679.[citado 2024 out. 09 ] Available from: https://doi.org/10.1016/s0042-207x(97)00067-5

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