ReP USP - Resultado da busca

Artigo de periodico
Efficient number of functional units and loop pipeline design Space exploration for high-level synthesis (2025)
Rosa, Leandro de Souza ; Bouganis, Christos-Savvas ; Bonato, Vanderlei
Source: Journal of the Brazilian Computer Society. Unidade: ICMC
Subjects: ARQUITETURA DE SOFTWARE, HARDWARE, PARETO OTIMALIDADE
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ROSA, Leandro de Souza e BOUGANIS, Christos-Savvas e BONATO, Vanderlei. Efficient number of functional units and loop pipeline design Space exploration for high-level synthesis. Journal of the Brazilian Computer Society, v. 31, n. 1, p. 570-582, 2025Tradução . . Disponível em: https://doi.org/10.5753/jbcs.2025.4912. Acesso em: 21 jan. 2026.
APA
Rosa, L. de S., Bouganis, C. -S., & Bonato, V. (2025). Efficient number of functional units and loop pipeline design Space exploration for high-level synthesis. Journal of the Brazilian Computer Society, 31( 1), 570-582. doi:10.5753/jbcs.2025.4912
NLM
Rosa L de S, Bouganis C-S, Bonato V. Efficient number of functional units and loop pipeline design Space exploration for high-level synthesis [Internet]. Journal of the Brazilian Computer Society. 2025 ; 31( 1): 570-582.[citado 2026 jan. 21 ] Available from: https://doi.org/10.5753/jbcs.2025.4912
Vancouver
Rosa L de S, Bouganis C-S, Bonato V. Efficient number of functional units and loop pipeline design Space exploration for high-level synthesis [Internet]. Journal of the Brazilian Computer Society. 2025 ; 31( 1): 570-582.[citado 2026 jan. 21 ] Available from: https://doi.org/10.5753/jbcs.2025.4912
Artigo de periodico
Fast resource and timing aware design optimisation for high-level synthesis (2021)
Perina, André Bannwart ; Silitonga, Arthur ; Becker, Jürgen ; Bonato, Vanderlei
Source: IEEE Transactions on Computers. Unidade: ICMC
Subjects: HARDWARE, ANÁLISE DE DESEMPENHO
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PERINA, André Bannwart et al. Fast resource and timing aware design optimisation for high-level synthesis. IEEE Transactions on Computers, v. 70, n. 12, p. 2070-2082, 2021Tradução . . Disponível em: https://doi.org/10.1109/TC.2021.3112260. Acesso em: 21 jan. 2026.
APA
Perina, A. B., Silitonga, A., Becker, J., & Bonato, V. (2021). Fast resource and timing aware design optimisation for high-level synthesis. IEEE Transactions on Computers, 70( 12), 2070-2082. doi:10.1109/TC.2021.3112260
NLM
Perina AB, Silitonga A, Becker J, Bonato V. Fast resource and timing aware design optimisation for high-level synthesis [Internet]. IEEE Transactions on Computers. 2021 ; 70( 12): 2070-2082.[citado 2026 jan. 21 ] Available from: https://doi.org/10.1109/TC.2021.3112260
Vancouver
Perina AB, Silitonga A, Becker J, Bonato V. Fast resource and timing aware design optimisation for high-level synthesis [Internet]. IEEE Transactions on Computers. 2021 ; 70( 12): 2070-2082.[citado 2026 jan. 21 ] Available from: https://doi.org/10.1109/TC.2021.3112260
Artigo de periodico
Scaling up modulo scheduling for high-level synthesis (2019)
Rosa, Leandro de Souza; Bouganis, Christos-Savvas; Bonato, Vanderlei
Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Unidade: ICMC
Subjects: CIRCUITOS FPGA, ALGORITMOS GENÉTICOS, COMPUTAÇÃO RECONFIGURÁVEL, ALGORITMOS DE SCHEDULING, SCHEDULING
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ROSA, Leandro de Souza e BOUGANIS, Christos-Savvas e BONATO, Vanderlei. Scaling up modulo scheduling for high-level synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v. 38, n. 5, p. 912-925, 2019Tradução . . Disponível em: https://doi.org/10.1109/TCAD.2018.2834440. Acesso em: 21 jan. 2026.
APA
Rosa, L. de S., Bouganis, C. -S., & Bonato, V. (2019). Scaling up modulo scheduling for high-level synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 38( 5), 912-925. doi:10.1109/TCAD.2018.2834440
NLM
Rosa L de S, Bouganis C-S, Bonato V. Scaling up modulo scheduling for high-level synthesis [Internet]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2019 ; 38( 5): 912-925.[citado 2026 jan. 21 ] Available from: https://doi.org/10.1109/TCAD.2018.2834440
Vancouver
Rosa L de S, Bouganis C-S, Bonato V. Scaling up modulo scheduling for high-level synthesis [Internet]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2019 ; 38( 5): 912-925.[citado 2026 jan. 21 ] Available from: https://doi.org/10.1109/TCAD.2018.2834440

USP Schools

ReP

Filtros

Authors

Subjects