ReP USP - Resultado da busca

Parte de monografia/livro
Temperature influence on the generation lifetime determination based on drain current transients in partially depleted SOI nMOSFETs (2004)
Martino, João Antonio ; Rafi, J.M.; Mercha, A.; Simoen, Eddy ; Claeys, Cor
Source: 8. Symposium on High Purity Silicon: proceedings. Conference titles: Symposium on High Purity Silicon. Unidade: EP
Subjects: MICROELETRÔNICA, CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MARTINO, João Antonio et al. Temperature influence on the generation lifetime determination based on drain current transients in partially depleted SOI nMOSFETs. 8. Symposium on High Purity Silicon: proceedings. Tradução . Pennington: The Electrochemical Society, 2004. . . Acesso em: 06 jul. 2024.
APA
Martino, J. A., Rafi, J. M., Mercha, A., Simoen, E., & Claeys, C. (2004). Temperature influence on the generation lifetime determination based on drain current transients in partially depleted SOI nMOSFETs. In 8. Symposium on High Purity Silicon: proceedings. Pennington: The Electrochemical Society.
NLM
Martino JA, Rafi JM, Mercha A, Simoen E, Claeys C. Temperature influence on the generation lifetime determination based on drain current transients in partially depleted SOI nMOSFETs. In: 8. Symposium on High Purity Silicon: proceedings. Pennington: The Electrochemical Society; 2004. [citado 2024 jul. 06 ]
Vancouver
Martino JA, Rafi JM, Mercha A, Simoen E, Claeys C. Temperature influence on the generation lifetime determination based on drain current transients in partially depleted SOI nMOSFETs. In: 8. Symposium on High Purity Silicon: proceedings. Pennington: The Electrochemical Society; 2004. [citado 2024 jul. 06 ]
Trabalho de evento
Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures (2004)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Microelectronic Technology and Devices SBMicro 2004. Proceedings, v. 2003-9. Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures. 2004, Anais.. Pennington: The Electrochemical Society, 2004. . Acesso em: 06 jul. 2024.
APA
Pavanello, M. A., Martino, J. A., Simoen, E., & Claeys, C. (2004). Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures. In Microelectronic Technology and Devices SBMicro 2004. Proceedings, v. 2003-9. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Martino JA, Simoen E, Claeys C. Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures. Microelectronic Technology and Devices SBMicro 2004. Proceedings, v. 2003-9. 2004 ;[citado 2024 jul. 06 ]
Vancouver
Pavanello MA, Martino JA, Simoen E, Claeys C. Evaluation of the channel engineering impact on the analog performance of deep-submicrometer partially depleted SOI MOSFETS at low temperatures. Microelectronic Technology and Devices SBMicro 2004. Proceedings, v. 2003-9. 2004 ;[citado 2024 jul. 06 ]
Trabalho de evento
An improved model for the triangular SOI misalignment test structure (2004)
Giacomini, Renato Camargo; Martino, João Antonio
Source: Microelectronics technology and devices SBMicro 2004. Proceedings, v. 2004-03. Conference titles: Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Subjects: MICROELETRÔNICA, ELETROQUÍMICA, CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
GIACOMINI, Renato Camargo e MARTINO, João Antonio. An improved model for the triangular SOI misalignment test structure. 2004, Anais.. Pennington: The Electrochemical Society, 2004. . Acesso em: 06 jul. 2024.
APA
Giacomini, R. C., & Martino, J. A. (2004). An improved model for the triangular SOI misalignment test structure. In Microelectronics technology and devices SBMicro 2004. Proceedings, v. 2004-03. Pennington: The Electrochemical Society.
NLM
Giacomini RC, Martino JA. An improved model for the triangular SOI misalignment test structure. Microelectronics technology and devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2024 jul. 06 ]
Vancouver
Giacomini RC, Martino JA. An improved model for the triangular SOI misalignment test structure. Microelectronics technology and devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2024 jul. 06 ]
Trabalho de evento
Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures (2004)
Pavanello, Marcelo Antonio ; Cerdeira, Antonio ; Martino, João Antonio ; Alemán, Miguel A; Flandre, Denis
Source: Microelectronic technology and devices SBMicro 2004. Proceedings, v. 2004-03. Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures. 2004, Anais.. Pennington: The Electrochemical Society, 2004. . Acesso em: 06 jul. 2024.
APA
Pavanello, M. A., Cerdeira, A., Martino, J. A., Alemán, M. A., & Flandre, D. (2004). Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures. In Microelectronic technology and devices SBMicro 2004. Proceedings, v. 2004-03. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Cerdeira A, Martino JA, Alemán MA, Flandre D. Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures. Microelectronic technology and devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2024 jul. 06 ]
Vancouver
Pavanello MA, Cerdeira A, Martino JA, Alemán MA, Flandre D. Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures. Microelectronic technology and devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2024 jul. 06 ]
Trabalho de evento
Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures (2004)
Santos, Carolina Davanzzo Gomes dos; Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis ; Raskin, Jean-Pierre
Source: Microelectronic technology and Devices SBMicro 2004. Proceedings, v. 2004-03. Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SANTOS, Carolina Davanzzo Gomes dos et al. Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures. 2004, Anais.. Pennington: The Electrochemical Society, 2004. . Acesso em: 06 jul. 2024.
APA
Santos, C. D. G. dos, Pavanello, M. A., Martino, J. A., Flandre, D., & Raskin, J. -P. (2004). Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures. In Microelectronic technology and Devices SBMicro 2004. Proceedings, v. 2004-03. Pennington: The Electrochemical Society.
NLM
Santos CDG dos, Pavanello MA, Martino JA, Flandre D, Raskin J-P. Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures. Microelectronic technology and Devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2024 jul. 06 ]
Vancouver
Santos CDG dos, Pavanello MA, Martino JA, Flandre D, Raskin J-P. Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures. Microelectronic technology and Devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2024 jul. 06 ]
Trabalho de evento
On-Resistance and harmonic distortion in graded-channel SOI FD MOSFET (2004)
Cerdeira, Antonio ; Alemán, Miguel A; Pavanello, Marcelo Antonio ; Martino, João Antonio ; Vancaillie, Laurent; Flandre, Denis
Source: ICCDCS 2004. Conference titles: IEEE International Caracas Conference on Devices, Circuits and Systems. Unidade: EP
Subjects: TRANSISTORES, CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
CERDEIRA, Antonio et al. On-Resistance and harmonic distortion in graded-channel SOI FD MOSFET. 2004, Anais.. New York: IEEE, 2004. . Acesso em: 06 jul. 2024.
APA
Cerdeira, A., Alemán, M. A., Pavanello, M. A., Martino, J. A., Vancaillie, L., & Flandre, D. (2004). On-Resistance and harmonic distortion in graded-channel SOI FD MOSFET. In ICCDCS 2004. New York: IEEE.
NLM
Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Vancaillie L, Flandre D. On-Resistance and harmonic distortion in graded-channel SOI FD MOSFET. ICCDCS 2004. 2004 ;[citado 2024 jul. 06 ]
Vancouver
Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Vancaillie L, Flandre D. On-Resistance and harmonic distortion in graded-channel SOI FD MOSFET. ICCDCS 2004. 2004 ;[citado 2024 jul. 06 ]

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