ReP USP - Resultado da busca

Trabalho de evento
Liquid helium temperature operation of graded-channel SOI nMOSFETs (2012)
Souza, Michelly de ; Kilchytska, Valeriya ; Flandre, Denis ; Pavanello, Marcelo Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SOUZA, Michelly de et al. Liquid helium temperature operation of graded-channel SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0135ecst. Acesso em: 03 jul. 2024.
APA
Souza, M. de, Kilchytska, V., Flandre, D., & Pavanello, M. A. (2012). Liquid helium temperature operation of graded-channel SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0135ecst
NLM
Souza M de, Kilchytska V, Flandre D, Pavanello MA. Liquid helium temperature operation of graded-channel SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 jul. 03 ] Available from: https://doi.org/10.1149/04901.0135ecst
Vancouver
Souza M de, Kilchytska V, Flandre D, Pavanello MA. Liquid helium temperature operation of graded-channel SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 jul. 03 ] Available from: https://doi.org/10.1149/04901.0135ecst
Trabalho de evento
High performance current mirrors using graded-channel SOI MOSFETs (2001)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: Proceedings. Conference titles: International Symposium on Silicon-on-Insulator Technology and Devices. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. High performance current mirrors using graded-channel SOI MOSFETs. 2001, Anais.. Pennington: The Electrochemical Society, 2001. . Acesso em: 03 jul. 2024.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2001). High performance current mirrors using graded-channel SOI MOSFETs. In Proceedings. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Martino JA, Flandre D. High performance current mirrors using graded-channel SOI MOSFETs. Proceedings. 2001 ;[citado 2024 jul. 03 ]
Vancouver
Pavanello MA, Martino JA, Flandre D. High performance current mirrors using graded-channel SOI MOSFETs. Proceedings. 2001 ;[citado 2024 jul. 03 ]
Trabalho de evento
Modeling of the leakage drain current in accumulation mode SOI pMOSFETs for high-temperature applications (2001)
Bellodi, Marcello; Iniguez, Benjamin; Flandre, Denis ; Martino, João Antonio
Source: Proceedings. Conference titles: International Symposium on Silicon-on-Insulator Technology and Devices. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BELLODI, Marcello et al. Modeling of the leakage drain current in accumulation mode SOI pMOSFETs for high-temperature applications. 2001, Anais.. Pennington: The Electrochemical Society, 2001. . Acesso em: 03 jul. 2024.
APA
Bellodi, M., Iniguez, B., Flandre, D., & Martino, J. A. (2001). Modeling of the leakage drain current in accumulation mode SOI pMOSFETs for high-temperature applications. In Proceedings. Pennington: The Electrochemical Society.
NLM
Bellodi M, Iniguez B, Flandre D, Martino JA. Modeling of the leakage drain current in accumulation mode SOI pMOSFETs for high-temperature applications. Proceedings. 2001 ;[citado 2024 jul. 03 ]
Vancouver
Bellodi M, Iniguez B, Flandre D, Martino JA. Modeling of the leakage drain current in accumulation mode SOI pMOSFETs for high-temperature applications. Proceedings. 2001 ;[citado 2024 jul. 03 ]
Trabalho de evento
Comparison of analog performance in conventional and graded-channel fully-depleted SOI MOSFETs (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: SBMicro 2000: proceedings. Conference titles: International Conference on Microelectronics and Packaging. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Comparison of analog performance in conventional and graded-channel fully-depleted SOI MOSFETs. 2000, Anais.. Manaus: SBMicro/UA/UFRGS/UNICAMP/USP, 2000. . Acesso em: 03 jul. 2024.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2000). Comparison of analog performance in conventional and graded-channel fully-depleted SOI MOSFETs. In SBMicro 2000: proceedings. Manaus: SBMicro/UA/UFRGS/UNICAMP/USP.
NLM
Pavanello MA, Martino JA, Flandre D. Comparison of analog performance in conventional and graded-channel fully-depleted SOI MOSFETs. SBMicro 2000: proceedings. 2000 ;[citado 2024 jul. 03 ]
Vancouver
Pavanello MA, Martino JA, Flandre D. Comparison of analog performance in conventional and graded-channel fully-depleted SOI MOSFETs. SBMicro 2000: proceedings. 2000 ;[citado 2024 jul. 03 ]
Trabalho de evento
Diodes model for the leakage drain current in enhancement-mode SOI nMOSFETs at 300 GRAUS C (2000)
Bellodi, Marcello; Iniguez, Benjamin; Flandre, Denis ; Martino, João Antonio
Source: SBMicro 2000 : proceedings. Conference titles: International Conference on Microelectronics and Packaging. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BELLODI, Marcello et al. Diodes model for the leakage drain current in enhancement-mode SOI nMOSFETs at 300 GRAUS C. 2000, Anais.. Manaus: SBMicro/UA/UFRGS/UNICAMP/USP, 2000. . Acesso em: 03 jul. 2024.
APA
Bellodi, M., Iniguez, B., Flandre, D., & Martino, J. A. (2000). Diodes model for the leakage drain current in enhancement-mode SOI nMOSFETs at 300 GRAUS C. In SBMicro 2000 : proceedings. Manaus: SBMicro/UA/UFRGS/UNICAMP/USP.
NLM
Bellodi M, Iniguez B, Flandre D, Martino JA. Diodes model for the leakage drain current in enhancement-mode SOI nMOSFETs at 300 GRAUS C. SBMicro 2000 : proceedings. 2000 ;[citado 2024 jul. 03 ]
Vancouver
Bellodi M, Iniguez B, Flandre D, Martino JA. Diodes model for the leakage drain current in enhancement-mode SOI nMOSFETs at 300 GRAUS C. SBMicro 2000 : proceedings. 2000 ;[citado 2024 jul. 03 ]
Artigo de periodico
Analog performance and application of graded-channel fully depleted SOI MOSFETs (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Dessard, Vincent; Flandre, Denis
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Analog performance and application of graded-channel fully depleted SOI MOSFETs. Solid-State Electronics, v. 44, n. 7, p. 1219-1222, 2000Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(00)00034-4. Acesso em: 03 jul. 2024.
APA
Pavanello, M. A., Martino, J. A., Dessard, V., & Flandre, D. (2000). Analog performance and application of graded-channel fully depleted SOI MOSFETs. Solid-State Electronics, 44( 7), 1219-1222. doi:10.1016/s0038-1101(00)00034-4
NLM
Pavanello MA, Martino JA, Dessard V, Flandre D. Analog performance and application of graded-channel fully depleted SOI MOSFETs [Internet]. Solid-State Electronics. 2000 ; 44( 7): 1219-1222.[citado 2024 jul. 03 ] Available from: https://doi.org/10.1016/s0038-1101(00)00034-4
Vancouver
Pavanello MA, Martino JA, Dessard V, Flandre D. Analog performance and application of graded-channel fully depleted SOI MOSFETs [Internet]. Solid-State Electronics. 2000 ; 44( 7): 1219-1222.[citado 2024 jul. 03 ] Available from: https://doi.org/10.1016/s0038-1101(00)00034-4
Trabalho de evento
Study of the deep-submicron SOI MOSFET leakage current behavior at high temperatures (2000)
Bellodi, Marcello; Iniguez, Benjamin; Raynaud, Cristine; Flandre, Denis ; Martino, João Antonio
Source: SBMicro 2000: proceedings. Conference titles: International Conference on Microelectronics and Packaging. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BELLODI, Marcello et al. Study of the deep-submicron SOI MOSFET leakage current behavior at high temperatures. 2000, Anais.. Manaus: SBMicro/UA/UFRGS/UNICAMP/USP, 2000. . Acesso em: 03 jul. 2024.
APA
Bellodi, M., Iniguez, B., Raynaud, C., Flandre, D., & Martino, J. A. (2000). Study of the deep-submicron SOI MOSFET leakage current behavior at high temperatures. In SBMicro 2000: proceedings. Manaus: SBMicro/UA/UFRGS/UNICAMP/USP.
NLM
Bellodi M, Iniguez B, Raynaud C, Flandre D, Martino JA. Study of the deep-submicron SOI MOSFET leakage current behavior at high temperatures. SBMicro 2000: proceedings. 2000 ;[citado 2024 jul. 03 ]
Vancouver
Bellodi M, Iniguez B, Raynaud C, Flandre D, Martino JA. Study of the deep-submicron SOI MOSFET leakage current behavior at high temperatures. SBMicro 2000: proceedings. 2000 ;[citado 2024 jul. 03 ]
Trabalho de evento
Parasitic bipolar effects in graded-channel fully-depleted silicon-on-insulator nMOSFET (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: SBMicro 2000: proceedings. Conference titles: International Conference on Microelectronics and Packaging. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Parasitic bipolar effects in graded-channel fully-depleted silicon-on-insulator nMOSFET. 2000, Anais.. Manaus: SBMicro/UA/UFRGS/UNICAMP/USP, 2000. . Acesso em: 03 jul. 2024.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2000). Parasitic bipolar effects in graded-channel fully-depleted silicon-on-insulator nMOSFET. In SBMicro 2000: proceedings. Manaus: SBMicro/UA/UFRGS/UNICAMP/USP.
NLM
Pavanello MA, Martino JA, Flandre D. Parasitic bipolar effects in graded-channel fully-depleted silicon-on-insulator nMOSFET. SBMicro 2000: proceedings. 2000 ;[citado 2024 jul. 03 ]
Vancouver
Pavanello MA, Martino JA, Flandre D. Parasitic bipolar effects in graded-channel fully-depleted silicon-on-insulator nMOSFET. SBMicro 2000: proceedings. 2000 ;[citado 2024 jul. 03 ]
Trabalho de evento
Comparison of floating-body effects in conventional and graded-channel fully-depleted silicon-on-insulator nMOSFETs (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: Proceedings. Conference titles: IEEE International Conference on Devices, Circuits and Syems. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Comparison of floating-body effects in conventional and graded-channel fully-depleted silicon-on-insulator nMOSFETs. 2000, Anais.. Piscataway: IEEE, 2000. . Acesso em: 03 jul. 2024.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2000). Comparison of floating-body effects in conventional and graded-channel fully-depleted silicon-on-insulator nMOSFETs. In Proceedings. Piscataway: IEEE.
NLM
Pavanello MA, Martino JA, Flandre D. Comparison of floating-body effects in conventional and graded-channel fully-depleted silicon-on-insulator nMOSFETs. Proceedings. 2000 ;[citado 2024 jul. 03 ]
Vancouver
Pavanello MA, Martino JA, Flandre D. Comparison of floating-body effects in conventional and graded-channel fully-depleted silicon-on-insulator nMOSFETs. Proceedings. 2000 ;[citado 2024 jul. 03 ]

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