Genetic algorithms and artificial neural networks to combinational circuit generation on reconfigurable hardware (2010)
- Authors:
- USP affiliated authors: SILVA, JORGE LUIZ E - ICMC ; OSÓRIO, FERNANDO SANTOS - ICMC
- Unidade: ICMC
- DOI: 10.1109/ReConFig.2010.25
- Subjects: SISTEMAS EMBUTIDOS; SISTEMAS ESPECIALISTAS; ROBÓTICA
- Language: Inglês
- Imprenta:
- Publisher: IEEE Computer Society
- Publisher place: Los Alamitos
- Date published: 2010
- ISBN: 9780769543147
- Source:
- Título: Proceedings
- Conference titles: International Conference on Reconfigurable Computing and FPGAs - ReConFig
- Este periódico é de acesso aberto
- Este artigo NÃO é de acesso aberto
-
ABNT
SILVA, Bruno A et al. Genetic algorithms and artificial neural networks to combinational circuit generation on reconfigurable hardware. 2010, Anais.. Los Alamitos: IEEE Computer Society, 2010. Disponível em: https://doi.org/10.1109/ReConFig.2010.25. Acesso em: 19 fev. 2026. -
APA
Silva, B. A., Dias, M. A., Silva, J. L. e, & Osório, F. S. (2010). Genetic algorithms and artificial neural networks to combinational circuit generation on reconfigurable hardware. In Proceedings. Los Alamitos: IEEE Computer Society. doi:10.1109/ReConFig.2010.25 -
NLM
Silva BA, Dias MA, Silva JL e, Osório FS. Genetic algorithms and artificial neural networks to combinational circuit generation on reconfigurable hardware [Internet]. Proceedings. 2010 ;[citado 2026 fev. 19 ] Available from: https://doi.org/10.1109/ReConFig.2010.25 -
Vancouver
Silva BA, Dias MA, Silva JL e, Osório FS. Genetic algorithms and artificial neural networks to combinational circuit generation on reconfigurable hardware [Internet]. Proceedings. 2010 ;[citado 2026 fev. 19 ] Available from: https://doi.org/10.1109/ReConFig.2010.25 - Research and partial analysis of overhead of a partition model for a partially reconfigurable hardware in a data-driven machine-chicflow
- A partition model using partial reconfigurable hardware for chipCflow project
- Tag management in a reconfigurable tagged-token dataflow architecture
- ChipCFlow: uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável - organização de memória
- Execution of algorithms using a dynamic dataflow model for reconfigurable hardware: commands in dataflow graph
- A benchmark approach for compilers in reconfigurable hardware
- RtrASSoc51-rI2C (reconfigurable inter integrated circuit)
- The ChipCflow: a tool to generate hardware accelerators using a static dataflow machine designed for a FPGA
- RtrASSoc51 - adaptable superscalar reconfigurable programmable system on chip: the reconfigurable tools for DSR a development system
- Execution of algorithms using a dynamic dataflow model for reconfigurable hardware: a purpose for matching data
Informações sobre o DOI: 10.1109/ReConFig.2010.25 (Fonte: oaDOI API)
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