RtrASSoc51 - adaptable superscalar reconfigurable programmable system on chip: the reconfigurable tools for DSR a development system (2005)
- Autor:
- Autor USP: SILVA, JORGE LUIZ E - ICMC
- Unidade: ICMC
- Subjects: SISTEMAS DISTRIBUÍDOS; PROGRAMAÇÃO CONCORRENTE
- Language: Inglês
- Imprenta:
- Source:
- Título do periódico: Proceedings
- Conference titles: IP Based Soc Design Conference & Exhibition - IP-SOC
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ABNT
SILVA, Jorge Luiz e. RtrASSoc51 - adaptable superscalar reconfigurable programmable system on chip: the reconfigurable tools for DSR a development system. 2005, Anais.. Grenoble: Instituto de Ciências Matemáticas e de Computação, Universidade de São Paulo, 2005. . Acesso em: 28 jul. 2024. -
APA
Silva, J. L. e. (2005). RtrASSoc51 - adaptable superscalar reconfigurable programmable system on chip: the reconfigurable tools for DSR a development system. In Proceedings. Grenoble: Instituto de Ciências Matemáticas e de Computação, Universidade de São Paulo. -
NLM
Silva JL e. RtrASSoc51 - adaptable superscalar reconfigurable programmable system on chip: the reconfigurable tools for DSR a development system. Proceedings. 2005 ;[citado 2024 jul. 28 ] -
Vancouver
Silva JL e. RtrASSoc51 - adaptable superscalar reconfigurable programmable system on chip: the reconfigurable tools for DSR a development system. Proceedings. 2005 ;[citado 2024 jul. 28 ] - A benchmark approach for compilers in reconfigurable hardware
- Research and partial analysis of overhead of a partition model for a partially reconfigurable hardware in a data-driven machine-chicflow
- A partition model using partial reconfigurable hardware for chipCflow project
- Tag management in a reconfigurable tagged-token dataflow architecture
- Execution of algorithms using a dynamic dataflow model for reconfigurable hardware: a purpose for matching data
- C commands Implemented direct into the hardware using the ChipCflow Machine
- A dynamic dataflow architecture using partial reconfigurable hardware as an option for multiple cores
- RtrASSoc51-rI2C (reconfigurable inter integrated circuit)
- The ChipCflow: a tool to generate hardware accelerators using a static dataflow machine designed for a FPGA
- ChipCFlow: uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável - organização de memória
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