Research and partial analysis of overhead of a partition model for a partially reconfigurable hardware in a data-driven machine-chicflow (2010)
- Autores:
- Autor USP: SILVA, JORGE LUIZ E - ICMC
- Unidade: ICMC
- DOI: 10.1109/SPL.2010.5483013
- Assuntos: SISTEMAS EMBUTIDOS; SISTEMAS ESPECIALISTAS; ROBÓTICA
- Idioma: Inglês
- Imprenta:
- Editora: IEEE
- Local: Piscataway
- Data de publicação: 2010
- ISBN: 9781424470891
- Fonte:
- Título do periódico: Proceedings
- Nome do evento: Southern Programmable Logic Conference - SPL
- Este periódico é de assinatura
- Este artigo NÃO é de acesso aberto
- Cor do Acesso Aberto: closed
-
ABNT
SOUZA JÚNIOR, Francisco de et al. Research and partial analysis of overhead of a partition model for a partially reconfigurable hardware in a data-driven machine-chicflow. 2010, Anais.. Piscataway: IEEE, 2010. Disponível em: https://doi.org/10.1109/SPL.2010.5483013. Acesso em: 19 set. 2024. -
APA
Souza Júnior, F. de, Silva, J. L. e, Sanches, L., & Astolfi, V. (2010). Research and partial analysis of overhead of a partition model for a partially reconfigurable hardware in a data-driven machine-chicflow. In Proceedings. Piscataway: IEEE. doi:10.1109/SPL.2010.5483013 -
NLM
Souza Júnior F de, Silva JL e, Sanches L, Astolfi V. Research and partial analysis of overhead of a partition model for a partially reconfigurable hardware in a data-driven machine-chicflow [Internet]. Proceedings. 2010 ;[citado 2024 set. 19 ] Available from: https://doi.org/10.1109/SPL.2010.5483013 -
Vancouver
Souza Júnior F de, Silva JL e, Sanches L, Astolfi V. Research and partial analysis of overhead of a partition model for a partially reconfigurable hardware in a data-driven machine-chicflow [Internet]. Proceedings. 2010 ;[citado 2024 set. 19 ] Available from: https://doi.org/10.1109/SPL.2010.5483013 - A benchmark approach for compilers in reconfigurable hardware
- A partition model using partial reconfigurable hardware for chipCflow project
- Tag management in a reconfigurable tagged-token dataflow architecture
- RtrASSoc51 - adaptable superscalar reconfigurable programmable system on chip: the reconfigurable tools for DSR a development system
- Execution of algorithms using a dynamic dataflow model for reconfigurable hardware: a purpose for matching data
- C commands Implemented direct into the hardware using the ChipCflow Machine
- A dynamic dataflow architecture using partial reconfigurable hardware as an option for multiple cores
- RtrASSoc51-rI2C (reconfigurable inter integrated circuit)
- The ChipCflow: a tool to generate hardware accelerators using a static dataflow machine designed for a FPGA
- ChipCFlow: uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável - organização de memória
Informações sobre o DOI: 10.1109/SPL.2010.5483013 (Fonte: oaDOI API)
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