ReP USP - Resultado da busca

Artigo de periodico
Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications (2023)
Silva, V C P; Martino, João Antonio ; Simoen, Eddy ; Veloso, Anabela; Agopian, Paula Ghedini Der
Fonte: Solid State Electronics. Unidade: EP
Assuntos: TRANSISTORES, TEMPERATURA, NANOTECNOLOGIA, CIRCUITOS ANALÓGICOS, CIRCUITOS DIGITAIS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SILVA, V C P et al. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications. Solid State Electronics, v. 208, p. 1-5, 2023Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108729. Acesso em: 05 dez. 2025.
APA
Silva, V. C. P., Martino, J. A., Simoen, E., Veloso, A., & Agopian, P. G. D. (2023). Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications. Solid State Electronics, 208, 1-5. doi:10.1016/j.sse.2023.108729
NLM
Silva VCP, Martino JA, Simoen E, Veloso A, Agopian PGD. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications [Internet]. Solid State Electronics. 2023 ;208 1-5.[citado 2025 dez. 05 ] Available from: https://doi.org/10.1016/j.sse.2023.108729
Vancouver
Silva VCP, Martino JA, Simoen E, Veloso A, Agopian PGD. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications [Internet]. Solid State Electronics. 2023 ;208 1-5.[citado 2025 dez. 05 ] Available from: https://doi.org/10.1016/j.sse.2023.108729
Artigo de periodico
Modeling and Analysis of Inductive -Kickback- in Low Voltage Circuits (2020)
Cipparrone, Flávio Almeida de Magalhães ; Kaiser, Walter ; Beccaro, Wesley
Fonte: IEEE Transactions on Education. Unidade: EP
Assuntos: CIRCUITOS DIGITAIS, CIRCUITOS ELÉTRICOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
CIPPARRONE, Flávio Almeida de Magalhães e KAISER, Walter e BECCARO, Wesley. Modeling and Analysis of Inductive -Kickback- in Low Voltage Circuits. IEEE Transactions on Education, v. 63, p. 17-23, 2020Tradução . . Disponível em: http://www.ieee.org/publications_standards/publications/rights/index.html for more information. Acesso em: 05 dez. 2025.
APA
Cipparrone, F. A. de M., Kaiser, W., & Beccaro, W. (2020). Modeling and Analysis of Inductive -Kickback- in Low Voltage Circuits. IEEE Transactions on Education, 63, 17-23. doi:10.1109/TE.2019.2929476
NLM
Cipparrone FA de M, Kaiser W, Beccaro W. Modeling and Analysis of Inductive -Kickback- in Low Voltage Circuits [Internet]. IEEE Transactions on Education. 2020 ; 63 17-23.[citado 2025 dez. 05 ] Available from: http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Vancouver
Cipparrone FA de M, Kaiser W, Beccaro W. Modeling and Analysis of Inductive -Kickback- in Low Voltage Circuits [Internet]. IEEE Transactions on Education. 2020 ; 63 17-23.[citado 2025 dez. 05 ] Available from: http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Trabalho de evento
Design of high speed digital circuits with E-TSPC cell library (2011)
Soares Junior, João Navarro ; Martins, Gustavo C.
Fonte: Anais. Nome do evento: Encontro da Sociedade Brasileira de Crescimento de Cristais - SBCC. Unidade: EESC
Assuntos: ENGENHARIA ELÉTRICA, CIRCUITOS DIGITAIS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SOARES JUNIOR, João Navarro e MARTINS, Gustavo C. Design of high speed digital circuits with E-TSPC cell library. 2011, Anais.. São Paulo, SP: SBCC, 2011. Disponível em: https://repositorio.usp.br/directbitstream/53d5be3f-d36f-48ba-a26a-758e4210b290/2020876.2020915.pdf. Acesso em: 05 dez. 2025.
APA
Soares Junior, J. N., & Martins, G. C. (2011). Design of high speed digital circuits with E-TSPC cell library. In Anais. São Paulo, SP: SBCC. Recuperado de https://repositorio.usp.br/directbitstream/53d5be3f-d36f-48ba-a26a-758e4210b290/2020876.2020915.pdf
NLM
Soares Junior JN, Martins GC. Design of high speed digital circuits with E-TSPC cell library [Internet]. Anais. 2011 ;[citado 2025 dez. 05 ] Available from: https://repositorio.usp.br/directbitstream/53d5be3f-d36f-48ba-a26a-758e4210b290/2020876.2020915.pdf
Vancouver
Soares Junior JN, Martins GC. Design of high speed digital circuits with E-TSPC cell library [Internet]. Anais. 2011 ;[citado 2025 dez. 05 ] Available from: https://repositorio.usp.br/directbitstream/53d5be3f-d36f-48ba-a26a-758e4210b290/2020876.2020915.pdf
Trabalho de evento
Color digital video acquisition and processing system using reconfigurable logic (2007)
Pedrino, Emerson Carlos; Roda, Valentin Obac; Jorge, Lúcio André de Castro; Francisco, Carlos Alberto de
Nome do evento: Southern Conference on Programmable Logic. Unidade: EESC
Assunto: CIRCUITOS DIGITAIS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PEDRINO, Emerson Carlos et al. Color digital video acquisition and processing system using reconfigurable logic. 2007, Anais.. Mar del Plata: Escola de Engenharia de São Carlos, Universidade de São Paulo, 2007. . Acesso em: 05 dez. 2025.
APA
Pedrino, E. C., Roda, V. O., Jorge, L. A. de C., & Francisco, C. A. de. (2007). Color digital video acquisition and processing system using reconfigurable logic. In . Mar del Plata: Escola de Engenharia de São Carlos, Universidade de São Paulo.
NLM
Pedrino EC, Roda VO, Jorge LA de C, Francisco CA de. Color digital video acquisition and processing system using reconfigurable logic. 2007 ;[citado 2025 dez. 05 ]
Vancouver
Pedrino EC, Roda VO, Jorge LA de C, Francisco CA de. Color digital video acquisition and processing system using reconfigurable logic. 2007 ;[citado 2025 dez. 05 ]
Artigo de periodico
Considering Second-Harmonic Terms in the Operation of the Phase Detector for Second-Order Phase-Locked Loop (2003)
Piqueira, José Roberto Castilho ; Monteiro, Luiz Henrique Alves
Fonte: IEEE Transactions on Circuits and Systems. Unidade: EP
Assunto: CIRCUITOS DIGITAIS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PIQUEIRA, José Roberto Castilho e MONTEIRO, Luiz Henrique Alves. Considering Second-Harmonic Terms in the Operation of the Phase Detector for Second-Order Phase-Locked Loop. IEEE Transactions on Circuits and Systems, v. 50, n. 6, p. 805-809, 2003Tradução . . Disponível em: https://doi.org/10.1109/tcsi.2003.812612. Acesso em: 05 dez. 2025.
APA
Piqueira, J. R. C., & Monteiro, L. H. A. (2003). Considering Second-Harmonic Terms in the Operation of the Phase Detector for Second-Order Phase-Locked Loop. IEEE Transactions on Circuits and Systems, 50( 6), 805-809. doi:10.1109/tcsi.2003.812612
NLM
Piqueira JRC, Monteiro LHA. Considering Second-Harmonic Terms in the Operation of the Phase Detector for Second-Order Phase-Locked Loop [Internet]. IEEE Transactions on Circuits and Systems. 2003 ; 50( 6): 805-809.[citado 2025 dez. 05 ] Available from: https://doi.org/10.1109/tcsi.2003.812612
Vancouver
Piqueira JRC, Monteiro LHA. Considering Second-Harmonic Terms in the Operation of the Phase Detector for Second-Order Phase-Locked Loop [Internet]. IEEE Transactions on Circuits and Systems. 2003 ; 50( 6): 805-809.[citado 2025 dez. 05 ] Available from: https://doi.org/10.1109/tcsi.2003.812612
Artigo de periodico
Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design (2002)
Soares Junior, João Navarro ; Van Noije, Wilhelmus Adrianus Maria
Fonte: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Unidade: EP
Assunto: CIRCUITOS DIGITAIS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SOARES JUNIOR, João Navarro e VAN NOIJE, Wilhelmus Adrianus Maria. Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v. 10, n. 3, p. 301-308, 2002Tradução . . Disponível em: https://doi.org/10.1109/tvlsi.2002.1043333. Acesso em: 05 dez. 2025.
APA
Soares Junior, J. N., & Van Noije, W. A. M. (2002). Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10( 3), 301-308. doi:10.1109/tvlsi.2002.1043333
NLM
Soares Junior JN, Van Noije WAM. Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design [Internet]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2002 ; 10( 3): 301-308.[citado 2025 dez. 05 ] Available from: https://doi.org/10.1109/tvlsi.2002.1043333
Vancouver
Soares Junior JN, Van Noije WAM. Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design [Internet]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2002 ; 10( 3): 301-308.[citado 2025 dez. 05 ] Available from: https://doi.org/10.1109/tvlsi.2002.1043333

Unidades USP

ReP

Filtros

Autores

Autores USP

Ano de publicação

Assuntos

Título da fonte