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Filtros : "CIRCUITOS DIGITAIS" "EP-PSI" Removido: "Southern Conference on Programmable Logic" Limpar

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  • Artigo de periodico

    Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications (2023)

    Silva, V C P; Martino, João Antonio ; Simoen, Eddy ; Veloso, Anabela; Agopian, Paula Ghedini Der

    Source: Solid State Electronics. Unidade: EP

    Subjects: TRANSISTORES, TEMPERATURA, NANOTECNOLOGIA, CIRCUITOS ANALÓGICOS, CIRCUITOS DIGITAIS

    PrivadoAcesso à fonteDOIHow to cite
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    • ABNT

      SILVA, V C P et al. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications. Solid State Electronics, v. 208, p. 1-5, 2023Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108729. Acesso em: 05 dez. 2025.

    • APA

      Silva, V. C. P., Martino, J. A., Simoen, E., Veloso, A., & Agopian, P. G. D. (2023). Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications. Solid State Electronics, 208, 1-5. doi:10.1016/j.sse.2023.108729

    • NLM

      Silva VCP, Martino JA, Simoen E, Veloso A, Agopian PGD. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications [Internet]. Solid State Electronics. 2023 ;208 1-5.[citado 2025 dez. 05 ] Available from: https://doi.org/10.1016/j.sse.2023.108729

    • Vancouver

      Silva VCP, Martino JA, Simoen E, Veloso A, Agopian PGD. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications [Internet]. Solid State Electronics. 2023 ;208 1-5.[citado 2025 dez. 05 ] Available from: https://doi.org/10.1016/j.sse.2023.108729

  • Artigo de periodico

    Tunnel-FET evolution and applications for analog circuits (2022)

    Agopian, Paula Ghedini Der ; Martino, João Antonio ; Simoen, Eddy ; Rooyackers, Rita ; Claeys, Cor

    Source: Journal of Integrated Circuits and Systems. Unidade: EP

    Subjects: TRANSISTORES, SENSOR, CIRCUITOS ANALÓGICOS, CIRCUITOS DIGITAIS

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    • ABNT

      AGOPIAN, Paula Ghedini Der et al. Tunnel-FET evolution and applications for analog circuits. Journal of Integrated Circuits and Systems, v. 17, n. 2, p. 1-7, 2022Tradução . . Disponível em: https://doi.org/10.29292/jics.v17i2.631. Acesso em: 05 dez. 2025.

    • APA

      Agopian, P. G. D., Martino, J. A., Simoen, E., Rooyackers, R., & Claeys, C. (2022). Tunnel-FET evolution and applications for analog circuits. Journal of Integrated Circuits and Systems, 17( 2), 1-7. doi:10.29292/jics.v17i2.631

    • NLM

      Agopian PGD, Martino JA, Simoen E, Rooyackers R, Claeys C. Tunnel-FET evolution and applications for analog circuits [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-7.[citado 2025 dez. 05 ] Available from: https://doi.org/10.29292/jics.v17i2.631

    • Vancouver

      Agopian PGD, Martino JA, Simoen E, Rooyackers R, Claeys C. Tunnel-FET evolution and applications for analog circuits [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-7.[citado 2025 dez. 05 ] Available from: https://doi.org/10.29292/jics.v17i2.631

  • Artigo de periodico

    Modeling and Analysis of Inductive -Kickback- in Low Voltage Circuits (2020)

    Cipparrone, Flávio Almeida de Magalhães ; Kaiser, Walter ; Beccaro, Wesley

    Source: IEEE Transactions on Education. Unidade: EP

    Subjects: CIRCUITOS DIGITAIS, CIRCUITOS ELÉTRICOS

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    • ABNT

      CIPPARRONE, Flávio Almeida de Magalhães e KAISER, Walter e BECCARO, Wesley. Modeling and Analysis of Inductive -Kickback- in Low Voltage Circuits. IEEE Transactions on Education, v. 63, p. 17-23, 2020Tradução . . Disponível em: http://www.ieee.org/publications_standards/publications/rights/index.html for more information. Acesso em: 05 dez. 2025.

    • APA

      Cipparrone, F. A. de M., Kaiser, W., & Beccaro, W. (2020). Modeling and Analysis of Inductive -Kickback- in Low Voltage Circuits. IEEE Transactions on Education, 63, 17-23. doi:10.1109/TE.2019.2929476

    • NLM

      Cipparrone FA de M, Kaiser W, Beccaro W. Modeling and Analysis of Inductive -Kickback- in Low Voltage Circuits [Internet]. IEEE Transactions on Education. 2020 ; 63 17-23.[citado 2025 dez. 05 ] Available from: http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

    • Vancouver

      Cipparrone FA de M, Kaiser W, Beccaro W. Modeling and Analysis of Inductive -Kickback- in Low Voltage Circuits [Internet]. IEEE Transactions on Education. 2020 ; 63 17-23.[citado 2025 dez. 05 ] Available from: http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

  • Artigo de periodico

    Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design (2002)

    Soares Junior, João Navarro ; Van Noije, Wilhelmus Adrianus Maria

    Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Unidade: EP

    Assunto: CIRCUITOS DIGITAIS

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    • ABNT

      SOARES JUNIOR, João Navarro e VAN NOIJE, Wilhelmus Adrianus Maria. Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v. 10, n. 3, p. 301-308, 2002Tradução . . Disponível em: https://doi.org/10.1109/tvlsi.2002.1043333. Acesso em: 05 dez. 2025.

    • APA

      Soares Junior, J. N., & Van Noije, W. A. M. (2002). Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10( 3), 301-308. doi:10.1109/tvlsi.2002.1043333

    • NLM

      Soares Junior JN, Van Noije WAM. Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design [Internet]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2002 ; 10( 3): 301-308.[citado 2025 dez. 05 ] Available from: https://doi.org/10.1109/tvlsi.2002.1043333

    • Vancouver

      Soares Junior JN, Van Noije WAM. Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design [Internet]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2002 ; 10( 3): 301-308.[citado 2025 dez. 05 ] Available from: https://doi.org/10.1109/tvlsi.2002.1043333
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