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Artigo de periodico
Analog circuit design using graded-channel silicon-on-insulator nMOSFETs (2002)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS ANALÓGICOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs. Solid-State Electronics, v. 46, n. 8, p. 1215-1225, 2002Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(02)00020-5. Acesso em: 18 ago. 2024.
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2002). Analog circuit design using graded-channel silicon-on-insulator nMOSFETs. Solid-State Electronics, 46( 8), 1215-1225. doi:10.1016/s0038-1101(02)00020-5
NLM
Pavanello MA, Martino JA, Flandre D. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs [Internet]. Solid-State Electronics. 2002 ; 46( 8): 1215-1225.[citado 2024 ago. 18 ] Available from: https://doi.org/10.1016/s0038-1101(02)00020-5
Vancouver
Pavanello MA, Martino JA, Flandre D. Analog circuit design using graded-channel silicon-on-insulator nMOSFETs [Internet]. Solid-State Electronics. 2002 ; 46( 8): 1215-1225.[citado 2024 ago. 18 ] Available from: https://doi.org/10.1016/s0038-1101(02)00020-5
Artigo de periodico
An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Dessard, Vincent; Flandre, Denis
Source: Electrochemical and Solid-State Letters. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics. Electrochemical and Solid-State Letters, v. 3, n. Ja 2000, p. 50-52, 2000Tradução . . Disponível em: https://doi.org/10.1149/1.1390955. Acesso em: 18 ago. 2024.
APA
Pavanello, M. A., Martino, J. A., Dessard, V., & Flandre, D. (2000). An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics. Electrochemical and Solid-State Letters, 3( Ja 2000), 50-52. doi:10.1149/1.1390955
NLM
Pavanello MA, Martino JA, Dessard V, Flandre D. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics [Internet]. Electrochemical and Solid-State Letters. 2000 ; 3( Ja 2000): 50-52.[citado 2024 ago. 18 ] Available from: https://doi.org/10.1149/1.1390955
Vancouver
Pavanello MA, Martino JA, Dessard V, Flandre D. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics [Internet]. Electrochemical and Solid-State Letters. 2000 ; 3( Ja 2000): 50-52.[citado 2024 ago. 18 ] Available from: https://doi.org/10.1149/1.1390955
Artigo de periodico
Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's (1999)
Pavanello, Marcelo Antonio ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's. Solid-State Electronics, 1999Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(99)00178-1. Acesso em: 18 ago. 2024.
APA
Pavanello, M. A., & Martino, J. A. (1999). Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's. Solid-State Electronics. doi:10.1016/s0038-1101(99)00178-1
NLM
Pavanello MA, Martino JA. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's [Internet]. Solid-State Electronics. 1999 ;[citado 2024 ago. 18 ] Available from: https://doi.org/10.1016/s0038-1101(99)00178-1
Vancouver
Pavanello MA, Martino JA. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's [Internet]. Solid-State Electronics. 1999 ;[citado 2024 ago. 18 ] Available from: https://doi.org/10.1016/s0038-1101(99)00178-1
Artigo de periodico
Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k (1997)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Colinge, Jean-Pierre
Source: Microelectronic Engineering. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k. Microelectronic Engineering, v. 36, n. 1-4, p. 375-378, 1997Tradução . . Disponível em: https://doi.org/10.1016/s0167-9317(97)00083-x. Acesso em: 18 ago. 2024.
APA
Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1997). Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k. Microelectronic Engineering, 36( 1-4), 375-378. doi:10.1016/s0167-9317(97)00083-x
NLM
Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k [Internet]. Microelectronic Engineering. 1997 ; 36( 1-4): 375-378.[citado 2024 ago. 18 ] Available from: https://doi.org/10.1016/s0167-9317(97)00083-x
Vancouver
Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k [Internet]. Microelectronic Engineering. 1997 ; 36( 1-4): 375-378.[citado 2024 ago. 18 ] Available from: https://doi.org/10.1016/s0167-9317(97)00083-x

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