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Artigo de periodico
Memory aware design optimisation for high-level synthesis (2024)
Perina, André Bannwart ; Becker, Jürgen ; Bonato, Vanderlei
Source: Journal of Signal Processing Systems. Unidade: ICMC
Subjects: COMPUTAÇÃO RECONFIGURÁVEL, CIRCUITOS FPGA, ARQUITETURA DE SOFTWARE
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PERINA, André Bannwart e BECKER, Jürgen e BONATO, Vanderlei. Memory aware design optimisation for high-level synthesis. Journal of Signal Processing Systems, v. No 2024, n. 11, p. 651-671, 2024Tradução . . Disponível em: https://doi.org/10.1007/s11265-024-01938-3. Acesso em: 29 jun. 2025.
APA
Perina, A. B., Becker, J., & Bonato, V. (2024). Memory aware design optimisation for high-level synthesis. Journal of Signal Processing Systems, No 2024( 11), 651-671. doi:10.1007/s11265-024-01938-3
NLM
Perina AB, Becker J, Bonato V. Memory aware design optimisation for high-level synthesis [Internet]. Journal of Signal Processing Systems. 2024 ; No 2024( 11): 651-671.[citado 2025 jun. 29 ] Available from: https://doi.org/10.1007/s11265-024-01938-3
Vancouver
Perina AB, Becker J, Bonato V. Memory aware design optimisation for high-level synthesis [Internet]. Journal of Signal Processing Systems. 2024 ; No 2024( 11): 651-671.[citado 2025 jun. 29 ] Available from: https://doi.org/10.1007/s11265-024-01938-3
Artigo de periodico
A FAST hardware decoder optimized for template features to obtain order book Data in low latency (2023)
Oliveira, Caio C. S ; Bonato, Vanderlei
Source: Journal of Signal Processing Systems. Unidades: ICMC, EESC
Subjects: HARDWARE, ANÁLISE DE DADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
OLIVEIRA, Caio C. S e BONATO, Vanderlei. A FAST hardware decoder optimized for template features to obtain order book Data in low latency. Journal of Signal Processing Systems, v. 95, p. 559-567, 2023Tradução . . Disponível em: https://doi.org/10.1007/s11265-023-01850-2. Acesso em: 29 jun. 2025.
APA
Oliveira, C. C. S., & Bonato, V. (2023). A FAST hardware decoder optimized for template features to obtain order book Data in low latency. Journal of Signal Processing Systems, 95, 559-567. doi:10.1007/s11265-023-01850-2
NLM
Oliveira CCS, Bonato V. A FAST hardware decoder optimized for template features to obtain order book Data in low latency [Internet]. Journal of Signal Processing Systems. 2023 ; 95 559-567.[citado 2025 jun. 29 ] Available from: https://doi.org/10.1007/s11265-023-01850-2
Vancouver
Oliveira CCS, Bonato V. A FAST hardware decoder optimized for template features to obtain order book Data in low latency [Internet]. Journal of Signal Processing Systems. 2023 ; 95 559-567.[citado 2025 jun. 29 ] Available from: https://doi.org/10.1007/s11265-023-01850-2
Artigo de periodico
A Faddeev systolic array for EKF-SLAM and its arithmetic data representation impact on FPGA (2018)
Rosa, Leandro de Souza; Dasu, Aravind; Diniz, Pedro C.; Bonato, Vanderlei
Source: Journal of Signal Processing Systems. Unidade: ICMC
Subjects: COMPUTAÇÃO RECONFIGURÁVEL, SISTEMAS EMBUTIDOS, ROBÓTICA, COMPUTAÇÃO EVOLUTIVA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ROSA, Leandro de Souza et al. A Faddeev systolic array for EKF-SLAM and its arithmetic data representation impact on FPGA. Journal of Signal Processing Systems, v. 90, n. 3, p. 357-369, 2018Tradução . . Disponível em: https://doi.org/10.1007/s11265-017-1243-9. Acesso em: 29 jun. 2025.
APA
Rosa, L. de S., Dasu, A., Diniz, P. C., & Bonato, V. (2018). A Faddeev systolic array for EKF-SLAM and its arithmetic data representation impact on FPGA. Journal of Signal Processing Systems, 90( 3), 357-369. doi:10.1007/s11265-017-1243-9
NLM
Rosa L de S, Dasu A, Diniz PC, Bonato V. A Faddeev systolic array for EKF-SLAM and its arithmetic data representation impact on FPGA [Internet]. Journal of Signal Processing Systems. 2018 ; 90( 3): 357-369.[citado 2025 jun. 29 ] Available from: https://doi.org/10.1007/s11265-017-1243-9
Vancouver
Rosa L de S, Dasu A, Diniz PC, Bonato V. A Faddeev systolic array for EKF-SLAM and its arithmetic data representation impact on FPGA [Internet]. Journal of Signal Processing Systems. 2018 ; 90( 3): 357-369.[citado 2025 jun. 29 ] Available from: https://doi.org/10.1007/s11265-017-1243-9
Artigo de periodico
A Mersenne twister hardware implementation for the Monte Carlo localization algorithm (2013)
Bonato, Vanderlei ; Mazzotti, Bruno F; Fernandes, Marcio Merino; Marques, Eduardo
Source: Journal of Signal Processing Systems. Unidade: ICMC
Subjects: ARQUITETURA E ORGANIZAÇÃO DE COMPUTADORES, SISTEMAS EMBUTIDOS, ROBÓTICA, COMPUTAÇÃO EVOLUTIVA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BONATO, Vanderlei et al. A Mersenne twister hardware implementation for the Monte Carlo localization algorithm. Journal of Signal Processing Systems, v. 70, n. 1, p. 75-85, 2013Tradução . . Disponível em: https://doi.org/10.1007/s11265-012-0661-y. Acesso em: 29 jun. 2025.
APA
Bonato, V., Mazzotti, B. F., Fernandes, M. M., & Marques, E. (2013). A Mersenne twister hardware implementation for the Monte Carlo localization algorithm. Journal of Signal Processing Systems, 70( 1), 75-85. doi:10.1007/s11265-012-0661-y
NLM
Bonato V, Mazzotti BF, Fernandes MM, Marques E. A Mersenne twister hardware implementation for the Monte Carlo localization algorithm [Internet]. Journal of Signal Processing Systems. 2013 ; 70( 1): 75-85.[citado 2025 jun. 29 ] Available from: https://doi.org/10.1007/s11265-012-0661-y
Vancouver
Bonato V, Mazzotti BF, Fernandes MM, Marques E. A Mersenne twister hardware implementation for the Monte Carlo localization algorithm [Internet]. Journal of Signal Processing Systems. 2013 ; 70( 1): 75-85.[citado 2025 jun. 29 ] Available from: https://doi.org/10.1007/s11265-012-0661-y

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