Obtaining fault trees through SysML diagrams: a MBSE approach for reliability analysis (2020)
- Authors:
- USP affiliated authors: SOUZA, GILBERTO FRANCISCO MARTHA DE - EP ; MELANI, ARTHUR HENRIQUE DE ANDRADE - EP
- Unidade: EP
- DOI: 10.1109/RAMS48030.2020.9153658
- Assunto: ELEMENTOS DE MÁQUINAS
- Language: Inglês
- Imprenta:
- Source:
- Título: Proceedings
- Conference titles: Annual Reliability and Maintainability Symposium
- Status:
- Nenhuma versão em acesso aberto identificada
-
ABNT
MELANI, Arthur Henrique de Andrade e SOUZA, Gilberto Francisco Martha de. Obtaining fault trees through SysML diagrams: a MBSE approach for reliability analysis. 2020, Anais.. New York: Escola Politécnica, Universidade de São Paulo, 2020. Disponível em: https://doi.org/10.1109/RAMS48030.2020.9153658. Acesso em: 15 abr. 2026. -
APA
Melani, A. H. de A., & Souza, G. F. M. de. (2020). Obtaining fault trees through SysML diagrams: a MBSE approach for reliability analysis. In Proceedings. New York: Escola Politécnica, Universidade de São Paulo. doi:10.1109/RAMS48030.2020.9153658 -
NLM
Melani AH de A, Souza GFM de. Obtaining fault trees through SysML diagrams: a MBSE approach for reliability analysis [Internet]. Proceedings. 2020 ;[citado 2026 abr. 15 ] Available from: https://doi.org/10.1109/RAMS48030.2020.9153658 -
Vancouver
Melani AH de A, Souza GFM de. Obtaining fault trees through SysML diagrams: a MBSE approach for reliability analysis [Internet]. Proceedings. 2020 ;[citado 2026 abr. 15 ] Available from: https://doi.org/10.1109/RAMS48030.2020.9153658 - Mapping SysML diagrams into bayesian networks: a systems engineering approach for fault diagnosis
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