Filtros : "CIRCUITOS INTEGRADOS MOS" "PAVANELLO, MARCELO ANTONIO" Limpar

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  • Source: IEEE Transactions on Electron Devices. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS MOS

    Acesso à fonteDOIHow to cite
    A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
    • ABNT

      CERDEIRA, Antonio et al. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor. IEEE Transactions on Electron Devices, v. 52, n. 5, p. 967-972, 2005Tradução . . Disponível em: https://doi.org/10.1109/ted.2005.846327. Acesso em: 17 nov. 2025.
    • APA

      Cerdeira, A., Alemán, M. A., Pavanello, M. A., Martino, J. A., Flandre, D., & Vancaillie, L. (2005). Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor. IEEE Transactions on Electron Devices, 52( 5), 967-972. doi:10.1109/ted.2005.846327
    • NLM

      Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Flandre D, Vancaillie L. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor [Internet]. IEEE Transactions on Electron Devices. 2005 ;52( 5): 967-972.[citado 2025 nov. 17 ] Available from: https://doi.org/10.1109/ted.2005.846327
    • Vancouver

      Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Flandre D, Vancaillie L. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor [Internet]. IEEE Transactions on Electron Devices. 2005 ;52( 5): 967-972.[citado 2025 nov. 17 ] Available from: https://doi.org/10.1109/ted.2005.846327
  • Source: Journal de Physique IV. Unidade: EP

    Assunto: CIRCUITOS INTEGRADOS MOS

    Acesso à fonteDOIHow to cite
    A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
    • ABNT

      PAVANELLO, Marcelo Antonio et al. Low temperature operation of graded-channel SOI nMOSFETs for analog applications. Journal de Physique IV, v. 12, n. 3, 2002Tradução . . Disponível em: https://doi.org/10.1051/jp420020030. Acesso em: 17 nov. 2025.
    • APA

      Pavanello, M. A., Agopian, P. G. D., Martino, J. A., & Flandre, D. (2002). Low temperature operation of graded-channel SOI nMOSFETs for analog applications. Journal de Physique IV, 12( 3). doi:10.1051/jp420020030
    • NLM

      Pavanello MA, Agopian PGD, Martino JA, Flandre D. Low temperature operation of graded-channel SOI nMOSFETs for analog applications [Internet]. Journal de Physique IV. 2002 ;12( 3):[citado 2025 nov. 17 ] Available from: https://doi.org/10.1051/jp420020030
    • Vancouver

      Pavanello MA, Agopian PGD, Martino JA, Flandre D. Low temperature operation of graded-channel SOI nMOSFETs for analog applications [Internet]. Journal de Physique IV. 2002 ;12( 3):[citado 2025 nov. 17 ] Available from: https://doi.org/10.1051/jp420020030

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