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Filtros : "Financiamento FAPESP" "Inglaterra" "BONATO, VANDERLEI" Limpar

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  • Artigo de periodico

    Efficient number of functional units and loop pipeline design Space exploration for high-level synthesis (2025)

    Rosa, Leandro de Souza ; Bouganis, Christos-Savvas ; Bonato, Vanderlei

    Fonte: Journal of the Brazilian Computer Society. Unidade: ICMC

    Assuntos: ARQUITETURA DE SOFTWARE, HARDWARE, PARETO OTIMALIDADE

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    • ABNT

      ROSA, Leandro de Souza e BOUGANIS, Christos-Savvas e BONATO, Vanderlei. Efficient number of functional units and loop pipeline design Space exploration for high-level synthesis. Journal of the Brazilian Computer Society, v. 31, n. 1, p. 570-582, 2025Tradução . . Disponível em: https://doi.org/10.5753/jbcs.2025.4912. Acesso em: 08 out. 2025.

    • APA

      Rosa, L. de S., Bouganis, C. -S., & Bonato, V. (2025). Efficient number of functional units and loop pipeline design Space exploration for high-level synthesis. Journal of the Brazilian Computer Society, 31( 1), 570-582. doi:10.5753/jbcs.2025.4912

    • NLM

      Rosa L de S, Bouganis C-S, Bonato V. Efficient number of functional units and loop pipeline design Space exploration for high-level synthesis [Internet]. Journal of the Brazilian Computer Society. 2025 ; 31( 1): 570-582.[citado 2025 out. 08 ] Available from: https://doi.org/10.5753/jbcs.2025.4912

    • Vancouver

      Rosa L de S, Bouganis C-S, Bonato V. Efficient number of functional units and loop pipeline design Space exploration for high-level synthesis [Internet]. Journal of the Brazilian Computer Society. 2025 ; 31( 1): 570-582.[citado 2025 out. 08 ] Available from: https://doi.org/10.5753/jbcs.2025.4912

  • Artigo de periodico

    Non-iterative SDC modulo scheduling for high-level synthesis (2021)

    Rosa, Leandro de Souza ; Bouganis, Christos-Savvas ; Bonato, Vanderlei

    Fonte: Microprocessors and Microsystems. Unidade: ICMC

    Assuntos: LAÇOS, HARDWARE, TEMPO

    PrivadoAcesso à fonteDOIComo citar
    A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas

    • ABNT

      ROSA, Leandro de Souza e BOUGANIS, Christos-Savvas e BONATO, Vanderlei. Non-iterative SDC modulo scheduling for high-level synthesis. Microprocessors and Microsystems, v. 86, p. 1-13, 2021Tradução . . Disponível em: https://doi.org/10.1016/j.micpro.2021.104334. Acesso em: 08 out. 2025.

    • APA

      Rosa, L. de S., Bouganis, C. -S., & Bonato, V. (2021). Non-iterative SDC modulo scheduling for high-level synthesis. Microprocessors and Microsystems, 86, 1-13. doi:10.1016/j.micpro.2021.104334

    • NLM

      Rosa L de S, Bouganis C-S, Bonato V. Non-iterative SDC modulo scheduling for high-level synthesis [Internet]. Microprocessors and Microsystems. 2021 ; 86 1-13.[citado 2025 out. 08 ] Available from: https://doi.org/10.1016/j.micpro.2021.104334

    • Vancouver

      Rosa L de S, Bouganis C-S, Bonato V. Non-iterative SDC modulo scheduling for high-level synthesis [Internet]. Microprocessors and Microsystems. 2021 ; 86 1-13.[citado 2025 out. 08 ] Available from: https://doi.org/10.1016/j.micpro.2021.104334
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